| /art/compiler/utils/mips/ |
| assembler_mips.h | 184 void Lhu(Register rt, Register rs, uint16_t imm16);
[all...] |
| assembler_mips.cc | 443 void MipsAssembler::Lhu(Register rt, Register rs, uint16_t imm16) {
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4.txt | 234 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 140 lhu $s3,-22851($v0)
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 156 lhu $s3,-22851($v0)
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 156 lhu $s3,-22851($v0)
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 157 lhu $s3,-22851($v0)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| lb.d | 387 0+0374 <[^>]*> lhu a0,0\(zero\)
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ChangeLog-2011 | 231 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
|
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | [all...] |
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.td | [all...] |
| MicroMipsInstrInfo.td | 742 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
[all...] |
| Mips64InstrInfo.td | 173 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-score7.c | 363 {"lhu", s7_D_ldst},
630 {"lhu", 0x24000000, 0x3e000000, 0x8000, Rd_rvalueRs_SI15, s7_do_ldst_insn},
631 {"lhu", 0x06000002, 0x3e000007, 0x8000, Rd_rvalueRs_preSI12, s7_do_ldst_insn},
632 {"lhu", 0x0e000002, 0x3e000007, 0x8000, Rd_rvalueRs_postSI12, s7_do_ldst_insn},
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 303 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 336 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 333 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 334 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 399 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/v8/src/mips/ |
| codegen-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| codegen-mips64.cc | [all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 440 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
[all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_mips.S | 201 #define FETCH_INST() lhu rINST, (rPC)
211 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \
219 lhu _dreg, ((_count)*2)(_sreg) ; \
227 #define PREFETCH_INST(_count) lhu rINST, ((_count)*2)(rPC)
238 lhu rINST, (rPC)
246 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC)
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 550 // lhu with negative data.
551 __ lhu(t3, MemOperand(a0, offsetof(T, si)) );
562 __ lhu(t5, MemOperand(a0, offsetof(T, si)) );
[all...] |
