HomeSort by relevance Sort by last modified time
    Searched full:mips32 (Results 101 - 125 of 557) sorted by null

1 2 3 45 6 7 8 91011>>

  /external/valgrind/gdbserver_tests/
nlself_invalidate.vgtest 7 prereq: test -e gdb && ( ../tests/arch_test amd64 || ../tests/arch_test mips32 || ../tests/arch_test mips64 )
  /external/valgrind/none/tests/
allexec_prepare_prereq 35 pair mips32 mips64
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/mips/
vpx_config.c 8 static const char* const cfg = "--force-target=mips32-android-gcc --disable-runtime-cpu-detect --sdk-path=/usr/local/google/home/hkuang/Downloads/android-ndk-r8e --disable-vp9-encoder --disable-examples --disable-docs --enable-realtime-only";
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/mips-dspr2/
vpx_config.c 8 static const char* const cfg = "--force-target=mips32-android-gcc --disable-runtime-cpu-detect --sdk-path=/usr/local/google/home/hkuang/Downloads/android-ndk-r8e --disable-vp9-encoder --enable-dspr2 --disable-examples --disable-docs --enable-realtime-only";
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
micromips@mips32-cp2.s 1 # Source file to test assembly of MIPS32-derived microMIPS cop2 instructions.
mips32-cp2.s 1 # source file to test assembly of mips32 cop2 instructions
ase-errors-1.l 4 .*:9: Warning: the `dsp' extension requires MIPS32 revision 2 or greater
12 .*:25: Warning: the `dspr2' extension requires MIPS32 revision 2 or greater
18 .*:39: Warning: the `mcu' extension requires MIPS32 revision 2 or greater
26 .*:58: Warning: the `mips3d' extension requires MIPS32 revision 2 or greater
29 .*:68: Warning: the `mt' extension requires MIPS32 revision 2 or greater
32 .*:77: Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
36 .*:88: Warning: the `virt' extension requires MIPS32 revision 2 or greater
41 .*:100: Warning: the `eva' extension requires MIPS32 revision 2 or greater
mips32-cp2.d 2 #name: MIPS MIPS32 cop2 instructions
5 # Check MIPS32 cop2 instruction assembly
micromips@mips32-cp2.d 2 #name: MIPS MIPS32 cop2 instructions
3 #source: micromips@mips32-cp2.s
6 # Check MIPS32 cop2 instruction assembly (microMIPS).
micromips@mips32.d 2 #name: MIPS MIPS32 instructions
3 #source: mips32.s
6 # Check MIPS32 instruction assembly (microMIPS).
  /external/llvm/lib/Target/Mips/
MipsSERegisterInfo.h 1 //===-- MipsSERegisterInfo.h - Mips32/64 Register Information ---*- C++ -*-===//
10 // This file contains the Mips32/64 implementation of the TargetRegisterInfo
MipsSubtarget.h 41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
98 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
104 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
128 // Allow mixed Mips16 and Mips32 in one source file
133 // compiled as Mips32
191 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
236 // native mips32 floating point instructions (those runtime routines
237 // run in mips32 hard float mode).
  /external/llvm/test/CodeGen/Mips/
fabs.ll 9 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s
11 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s
fneg.ll 9 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s
11 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s
selectcc.ll 1 ; RUN: llc -march=mipsel -mcpu=mips32 < %s
2 ; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
fp16mix.ll 1 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=10 -mips-os16 < %s | FileCheck %s -check-prefix=fmask1
3 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=01 -mips-os16 < %s | FileCheck %s -check-prefix=fmask2
5 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=10. -mips-os16 < %s | FileCheck %s -check-prefix=fmask1nr
fpnotneeded.ll 1 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-os16 | FileCheck %s -check-prefix=32
3 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=static -O3 -mips16-constant-islands < %s -mips-os16 | FileCheck %s -check-prefix=cisle
  /external/llvm/test/MC/Mips/mips32/
abiflags.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
  /external/valgrind/drd/tests/
Makefile.am 71 annotate_trace_memory.stderr.exp-mips32 \
75 annotate_trace_memory_xml.stderr.exp-mips32 \
103 fp_race.stderr.exp-mips32-be \
104 fp_race.stderr.exp-mips32-le \
109 fp_race_xml.stderr.exp-mips32-be \
110 fp_race_xml.stderr.exp-mips32-le \
232 sem_as_mutex.stderr.exp-mips32-be \
233 sem_as_mutex.stderr.exp-mips32-le \
238 sem_as_mutex3.stderr.exp-mips32-be \
239 sem_as_mutex3.stderr.exp-mips32-le
    [all...]
  /external/llvm/test/CodeGen/Mips/msa/
basic_operations.ll 1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-BE %s
2 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s
149 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
156 ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
185 ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
186 ; MIPS32-DAG: insert.b [[R1]][4], [[R2]]
188 ; MIPS32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
189 ; MIPS32-DAG: insert.b [[R1]][5], [[R3]]
191 ; MIPS32-DAG: lw [[R4:\$[0-9]+]], 24($sp)
192 ; MIPS32-DAG: insert.b [[R1]][6], [[R4]
    [all...]
  /external/valgrind/include/
Makefile.am 58 vki/vki-posixtypes-mips32-linux.h \
67 vki/vki-mips32-linux.h \
76 vki/vki-scnums-mips32-linux.h \
  /external/valgrind/helgrind/tests/
Makefile.am 93 tc18_semabuse.stderr.exp-linux-mips32 \
94 tc18_semabuse.stderr.exp-linux-mips32-b \
97 tc19_shadowmem.stderr.exp tc19_shadowmem.stderr.exp-mips32 \
102 tc20_verifywrap.stderr.exp-mips32 \
103 tc20_verifywrap.stderr.exp-mips32-b \
113 tc23_bogus_condwait.stderr.exp-mips32 \
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/
mips-elf-flags.exp 141 isa_conflict { "-mips3 -mgp32 -32" "-mips32 -32" } 4000 isa32
149 regsize_conflict { "-mips32 -32" "-mips64 -mabi=o64" }
157 good_combination { "-mips2 -32" "-mips32 -32" "-mips32r2 -32" } { mips32r2 }
158 good_combination { "-mips1 -32" "-mips32r2 -32" "-mips32 -32" } { mips32r2 }
168 good_combination { "-mips32 -mabi=32" "-march=sb1 -mabi=32" } { sb1 o32 }
169 good_combination { "-mips64r2 -mabi=32" "-mips32 -mabi=32" } { mips64r2 o32 }
  /external/llvm/test/MC/Mips/
insn-directive.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | FileCheck %s --check-prefix=ASM
3 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
nooddspreg-cmdarg.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg -filetype=obj -o - | \

Completed in 355 milliseconds

1 2 3 45 6 7 8 91011>>