| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb.d | 40 0+03a <[^>]+> 436c muls r4, r5
|
| wince_inst.d | 117 0+19c <[^>]*> e0110392 ? muls r1, r2, r3
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| avr.h | 283 AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200)
|
| h8300.h | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| sh-opc.h | 658 /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up},
659 /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up},
[all...] |
| sh64-opc.c | 549 /* 000001mmmmmm1110nnnnnndddddd0000 muls.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
550 { "muls.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040e0000
[all...] |
| cris-opc.c | 823 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
[all...] |
| ChangeLog-0001 | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 26 // multiplies and FMADD/FMAs, as well as vector (floating point only) muls and
652 // For simplicity we only chain together sequences of MULs/MLAs where the
|
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 423 muls r1, r2, r1
424 muls r2, r2, r3
425 muls r3, r4
427 @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
428 @ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43]
429 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-cris.c | 209 /* Whether to emit error when a MULS/MULU could be located last on a
247 3. MULS/MULU
341 /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 532 TEST_F(AssemblerMIPSTest, MulS) {
533 DriverStr(RepeatFFF(&mips::MipsAssembler::MulS, "mul.s ${reg1}, ${reg2}, ${reg3}"), "MulS");
[all...] |
| assembler_mips.h | 247 void MulS(FRegister fd, FRegister fs, FRegister ft);
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 238 void MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
|
| /external/llvm/lib/Transforms/Scalar/ |
| NaryReassociate.cpp | 74 // 1) We only considers n-ary adds and muls for now. This should be extended
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target_nv50.cpp | 316 // 32-bit MUL will be split into 16-bit MULs
|
| /system/core/libpixelflinger/include/private/pixelflinger/ |
| ggl_context.h | 89 // 32 bit muls will loose the sign bit)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/sh64/ |
| basic-1.d | 234 [ ]+384:[ ]+047ed510[ ]+muls\.l r7,r53,r17
|
| /external/valgrind/none/tests/arm/ |
| v6intARM.stdout.exp | [all...] |
| v6intThumb.c | 798 printf("MULS\n");
799 TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
800 TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
801 TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
802 TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
803 TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
804 TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| cris.cpu | [all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| thumb1.txt | 296 # CHECK: muls r1, r2, r1
297 # CHECK: muls r3, r4
|
| /external/v8/src/crankshaft/mips64/ |
| lithium-mips64.h | 122 V(MulS) \
769 DECLARE_CONCRETE_INSTRUCTION(MulS, "mul-s")
[all...] |
| /external/hyphenation-patterns/et/ |
| hyph-et.pat.txt | 1960 4muls
|
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleSwift.td | 219 (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
[all...] |
