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  /external/llvm/test/MC/AArch64/
arm64-advsimd.s 608 shll.8h v1, v2, #8
609 shll.4s v3, v4, #16
610 shll.2d v5, v6, #32
614 shll v1.8h, v2.8b, #8
615 shll v1.4s, v2.4h, #16
616 shll v1.2d, v2.2s, #32
658 ; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e]
659 ; CHECK: shll.4s v3, v4, #16 ; encoding: [0x83,0x38,0x61,0x2e]
660 ; CHECK: shll.2d v5, v6, #32 ; encoding: [0xc5,0x38,0xa1,0x2e]
664 ; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e
    [all...]
neon-simd-misc.s 408 shll v2.8h, v4.8b, #8
409 shll v6.4s, v8.4h, #16
410 shll v6.2d, v8.2s, #32
415 // CHECK: shll v2.8h, v4.8b, #8 // encoding: [0x82,0x38,0x21,0x2e]
416 // CHECK: shll v6.4s, v8.4h, #16 // encoding: [0x06,0x39,0x61,0x2e]
417 // CHECK: shll v6.2d, v8.2s, #32 // encoding: [0x06,0x39,0xa1,0x2e]
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/
sh2a.s 150 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    [all...]
sh3-dsp.s 159 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    [all...]
sh4al-dsp.s 210 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    [all...]
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/
sh2a.s 150 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    [all...]
sh3-dsp.s 159 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    [all...]
sh4al-dsp.s 210 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
    [all...]
  /art/compiler/utils/x86/
assembler_x86.cc 1385 void X86Assembler::shll(Register reg, const Immediate& imm) function in class:art::x86::X86Assembler
1390 void X86Assembler::shll(Register operand, Register shifter) { function in class:art::x86::X86Assembler
1395 void X86Assembler::shll(const Address& address, const Immediate& imm) { function in class:art::x86::X86Assembler
1400 void X86Assembler::shll(const Address& address, Register shifter) { function in class:art::x86::X86Assembler
    [all...]
  /bionic/libm/x86/
e_exp.S 118 shll $4, %ecx
  /external/neven/Embedded/common/src/b_BitFeatureEm/
LocalScanner.c 703 uint32 shlL = 32 - offL;
704 for( iL = 0; iL < sizeL; iL++ ) dstL[ iL ] = ( dstL[ iL ] >> 1 ) | ( srcL[ iL ] << shlL );
755 uint32 shlL = 32 - offL;
756 for( iL = 0; iL < sizeL; iL++ ) dstL[ iL ] = ( src0L[ iL ] >> offL ) | ( src1L[ iL ] << shlL );
  /external/zlib/src/contrib/amd64/
amd64-match.S 179 shll $16, %chainlenwmask
  /external/zlib/src/contrib/asm686/
match.S 135 shll $16, %ebx
  /prebuilts/go/darwin-x86/src/crypto/sha256/
sha256block_386.s 148 SHLL $6, DX
  /prebuilts/go/darwin-x86/src/runtime/
sys_linux_386.s 439 SHLL $3, AX
  /prebuilts/go/linux-x86/src/crypto/sha256/
sha256block_386.s 148 SHLL $6, DX
  /prebuilts/go/linux-x86/src/runtime/
sys_linux_386.s 439 SHLL $3, AX
  /toolchain/binutils/binutils-2.25/gas/doc/
c-sh.texi 326 shll Rn swap.w Rm,Rn
  /art/compiler/utils/x86_64/
assembler_x86_64.h 591 void shll(CpuRegister reg, const Immediate& imm);
592 void shll(CpuRegister operand, CpuRegister shifter);
    [all...]
  /external/llvm/test/MC/X86/
x86-16.s 45 // CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]
47 // CHECK: shll %eax # encoding: [0x66,0xd1,0xe0]
x86-32.s 94 // CHECK: shll %eax # encoding: [0xd1,0xe0]
96 // CHECK: shll %eax # encoding: [0xd1,0xe0]
x86-32-coverage.s     [all...]
x86-64.s 96 // CHECK: shll $2, %eax
97 shll $2, %eax
99 // CHECK: shll $2, %eax
  /external/clang/test/CodeGen/
aarch64-neon-misc.c     [all...]
  /external/valgrind/VEX/orig_x86/
exit42.orig 262 0x3A965E4B: shll $0x4, %eax
297 0x3A965E4B: shll $0x4, %eax
430 0x3A972EA8: shll %cl, %eax
471 0x3A972EA8: shll %cl, %eax
530 0x3A972EA8: shll %cl, %eax
611 0x3A972F46: shll $0x8, %edi
    [all...]

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