| /external/llvm/test/MC/AArch64/ |
| neon-shift.s | 9 sshl v0.8b, v1.8b, v2.8b
10 sshl v0.16b, v1.16b, v2.16b
11 sshl v0.4h, v1.4h, v2.4h
12 sshl v0.8h, v1.8h, v2.8h
13 sshl v0.2s, v1.2s, v2.2s
14 sshl v0.4s, v1.4s, v2.4s
15 sshl v0.2d, v1.2d, v2.2d
17 // CHECK: sshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x44,0x22,0x0e]
18 // CHECK: sshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x44,0x22,0x4e]
19 // CHECK: sshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x44,0x62,0x0e
[all...] |
| neon-scalar-shift.s | 6 sshl d17, d31, d8
8 // CHECK: sshl d17, d31, d8 // encoding: [0xf1,0x47,0xe8,0x5e]
|
| /external/libhevc/common/arm64/ |
| ihevc_intra_pred_luma_planar.s | 209 sshl v27.8h, v27.8h, v29.8h //(1)shr
226 sshl v30.8h, v30.8h, v29.8h //(2)shr
243 sshl v28.8h, v28.8h, v29.8h //(3)shr
260 sshl v25.8h, v25.8h, v29.8h //(4)shr
276 sshl v16.8h, v16.8h, v29.8h //(5)shr
293 sshl v18.8h, v18.8h, v29.8h //(6)shr
309 sshl v26.8h, v26.8h, v29.8h //(7)shr
348 sshl v24.8h, v24.8h, v29.8h //(8)shr
382 sshl v27.8h, v27.8h, v29.8h //(1)shr
402 sshl v30.8h, v30.8h, v29.8h //(2)sh
[all...] |
| ihevc_intra_pred_chroma_planar.s | 213 sshl v12.8h, v12.8h, v14.8h //shr
217 sshl v28.8h, v28.8h, v14.8h
237 sshl v26.8h, v26.8h, v14.8h //shr
243 sshl v24.8h, v24.8h, v14.8h
263 sshl v22.8h, v22.8h, v14.8h //shr
278 sshl v20.8h, v20.8h, v14.8h
289 sshl v12.8h, v12.8h, v14.8h //shr
291 sshl v28.8h, v28.8h, v14.8h
|
| ihevc_weighted_pred_uni.s | 183 sshl v4.4s,v4.4s,v28.4s
193 sshl v6.4s,v6.4s,v28.4s
199 sshl v7.4s,v7.4s,v28.4s
208 sshl v16.4s,v16.4s,v28.4s
|
| ihevc_weighted_pred_bi.s | 237 sshl v4.4s,v4.4s,v28.4s //vshlq_s32(i4_tmp1_t1, tmp_shift_t)
249 sshl v6.4s,v6.4s,v28.4s
259 sshl v19.4s,v19.4s,v28.4s
271 sshl v18.4s,v18.4s,v28.4s
|
| ihevc_intra_pred_luma_dc.s | 195 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
448 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
|
| /external/libavc/common/armv8/ |
| ih264_ihadamard_scaling_av8.s | 149 sshl v0.4s, v0.4s, v14.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
150 sshl v1.4s, v1.4s, v14.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
151 sshl v2.4s, v2.4s, v14.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
152 sshl v3.4s, v3.4s, v14.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
239 sshl v2.4s, v2.4s, v28.4s
240 sshl v3.4s, v3.4s, v28.4s
|
| ih264_iquant_itrans_recon_av8.s | 150 sshl v0.4s, v0.4s, v30.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
151 sshl v2.4s, v2.4s, v30.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
152 sshl v4.4s, v4.4s, v30.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
153 sshl v6.4s, v6.4s, v30.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
341 sshl v0.4s, v0.4s, v30.4s // q0 = q[i] = (p[i] << (qp/6)) where i = 0..3
342 sshl v2.4s, v2.4s, v30.4s // q1 = q[i] = (p[i] << (qp/6)) where i = 4..7
343 sshl v4.4s, v4.4s, v30.4s // q2 = q[i] = (p[i] << (qp/6)) where i = 8..11
344 sshl v6.4s, v6.4s, v30.4s // q3 = q[i] = (p[i] << (qp/6)) where i = 12..15
573 sshl v16.4s, v16.4s, v0.4s
574 sshl v17.4s, v17.4s, v0.4
[all...] |
| ih264_iquant_itrans_recon_dc_av8.s | 140 sshl v0.4s, v0.4s, v30.4s
352 sshl v0.4s, v0.4s, v3.4s
|
| ih264_resi_trans_quant_av8.s | 205 sshl v20.4s, v20.4s, v24.4s //shift row 1
206 sshl v21.4s, v21.4s, v24.4s //shift row 2
207 sshl v22.4s, v22.4s, v24.4s //shift row 3
208 sshl v23.4s, v23.4s, v24.4s //shift row 4
428 sshl v20.4s, v20.4s, v24.4s //shift row 1
429 sshl v21.4s, v21.4s, v24.4s //shift row 2
430 sshl v22.4s, v22.4s, v24.4s //shift row 3
431 sshl v23.4s, v23.4s, v24.4s //shift row 4
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vshr.ll | 6 ; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
22 ; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic6x/ |
| insns16-s-unit.d | 93 [0-9a-f]+[02468ace] <[^>]*> 8c42[ \t]+sshl \.S1 a0,12,a0
94 [0-9a-f]+[02468ace] <[^>]*> 7d43[ \t]+sshl \.S2 b2,27,b2
95 [0-9a-f]+[02468ace] <[^>]*> 66c2[ \t]+sshl \.S1 a5,3,a5
96 [0-9a-f]+[02468ace] <[^>]*> 57c3[ \t]+sshl \.S2 b7,18,b7
97 [0-9a-f]+[02468ace] <[^>]*> 4442[ \t]+sshl \.S1 a0,2,a0
98 [0-9a-f]+[02468ace] <[^>]*> 3543[ \t]+sshl \.S2 b2,17,b2
111 [0-9a-f]+[02468ace] <[^>]*> 7fe3[ \t]+sshl \.S2 b7,b3,b7
112 [0-9a-f]+[02468ace] <[^>]*> 5ce2[ \t]+sshl \.S1 a1,a2,a1
113 [0-9a-f]+[02468ace] <[^>]*> 3de3[ \t]+sshl \.S2 b3,b1,b3
|
| insns-bad-1.s | 1100 sshl .L1 a0,a0,a0
1101 sshl .S1 a0,a0
1102 sshl .S1 a0,b0,a0
1103 sshl .S1X a0,a0,a0
1104 sshl .S2 b0,-1,b0
1105 sshl .S2 b0,32,b0
|
| insns-c674x.s | 1244 sshl .S1 a1,a2,a3
1245 [!b0] sshl .S1X b4,a5,a6
1246 [a1] sshl .S2 b7,b8,b9
1247 sshl .S2X a10,b11,b12
1248 sshl .S1 a13,31,a14
1249 [b1] sshl .S1X b15,0,a16
1250 [!a1] sshl .S2 b17,25,b18
1251 sshl .S2X a19,7,b20
[all...] |
| insns-bad-1.l | [all...] |
| insns-c674x.d | [all...] |
| /external/clang/test/CodeGen/ |
| arm64-scalar-test.c | 162 // CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.cc | [all...] |
| logic-a64.cc | 1877 LogicVRegister Simulator::sshl(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| disasm-a64.cc | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 484 // SSHL,USHL are WriteV.
|
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
