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  /external/v8/test/cctest/
test-disasm-x64.cc 403 __ subss(xmm1, xmm0);
404 __ subss(xmm1, Operand(rbx, rcx, times_4, 10000));
test-assembler-x64.cc 1041 __ subss(xmm3, xmm2); // Expected result in xmm3
    [all...]
test-assembler-ia32.cc 894 __ subss(xmm3, xmm2); // Expected result in xmm3
992 __ subss(xmm3, xmm2); // Expected result in xmm3
    [all...]
  /external/valgrind/none/tests/amd64/
insn_sse.def 141 subss xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
142 subss m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
  /external/valgrind/none/tests/x86/
insn_sse.def 141 subss xmm.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
142 subss m128.ps[12.34,56.77,43.21,87.65] xmm.ps[44.0,33.0,22.0,11.0] => 1.ps[31.66,33.0,22.0,11.0]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
simd-intel.d 74 [ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[eax\]
167 [ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[eax\]
simd-suffix.d 74 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
167 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
simd.d 73 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
166 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
x86-64-simd-intel.d 94 [ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
213 [ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
x86-64-simd-suffix.d 94 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
213 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
x86-64-simd.d 93 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
212 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
  /art/compiler/utils/x86_64/
assembler_x86_64_test.cc     [all...]
assembler_x86_64.h 408 void subss(XmmRegister dst, XmmRegister src);
409 void subss(XmmRegister dst, const Address& src);
    [all...]
  /external/llvm/test/CodeGen/X86/
half.ll 125 ; CHECK-LIBCALL-NEXT: subss [[REG1]], [[REG2]]
sse-intrinsics-x86.ll 246 ; CHECK: subss
  /external/valgrind/memcheck/tests/amd64/
sse_memory.c 246 TEST_INSN( &AllMask, SS,subss)
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/
x86-64-simd-intel.d 94 [ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
213 [ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
x86-64-simd-suffix.d 94 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
213 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
x86-64-simd.d 94 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
213 [ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
  /external/v8/src/ia32/
assembler-ia32.h 917 void subss(XMMRegister dst, XMMRegister src) { subss(dst, Operand(src)); }
918 void subss(XMMRegister dst, const Operand& src);
    [all...]
  /art/compiler/utils/x86/
assembler_x86.cc 416 void X86Assembler::subss(XmmRegister dst, XmmRegister src) { function in class:art::x86::X86Assembler
425 void X86Assembler::subss(XmmRegister dst, const Address& src) { function in class:art::x86::X86Assembler
    [all...]
  /external/llvm/test/MC/X86/
x86-32-coverage.s     [all...]
  /external/elfutils/tests/
testfile44.expect.bz2 
  /external/libvpx/libvpx/third_party/libyuv/source/
x86inc.asm 1088 AVX_INSTR subss, 1, 0, 0
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/third_party/x86inc/
x86inc.asm 1155 AVX_INSTR subss, 1, 0, 0

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