| /external/v8/src/mips/ |
| assembler-mips.cc | 2127 void Assembler::swc1(FPURegister fd, const MemOperand& src) { function in class:v8::internal::Assembler
[all...] |
| constants-mips.h | 379 SWC1 = ((7U << 3) + 1) << kOpcodeShift,
905 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
[all...] |
| disasm-mips.cc | [all...] |
| /external/llvm/test/MC/Mips/ |
| mips-fpu-instructions.s | 154 # CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
189 swc1 $f9,9158($a3)
|
| target-soft-float.s | 325 swc1 $f2, 16($7)
326 # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
|
| /external/llvm/test/CodeGen/Mips/ |
| return-vector.ll | 183 ; CHECK-DAG: swc1 $[[R0]], 12($4)
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 110 0xef 0xde 0x06 0xe7 # CHECK: swc1 $f6, -8465($24)
|
| valid-mips1.txt | 114 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 132 0xef 0xde 0x06 0xe7 # CHECK: swc1 $f6, -8465($24)
|
| valid-mips2.txt | 174 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 142 swc1 $f6,-8465($24)
|
| /art/compiler/jni/ |
| jni_cfi_test_expected.inc | 365 // 0x0000002c: swc1 f12, +72(r29)
438 // 0x00000030: swc1 f14, +124(r29)
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
202 Opc = Mips::SWC1;
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| sb.d | 390 0+0380 <[^>]*> swc1 \$f4,0\(zero\)
393 0+038c <[^>]*> swc1 \$f4,0\(zero\)
|
| /art/compiler/utils/mips/ |
| assembler_mips.cc | [all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 332 0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
333 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 365 0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
366 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 362 0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
363 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 363 0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
364 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 437 0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
438 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24)
|
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 373 SWC1 = ((7U << 3) + 1) << kOpcodeShift,
952 OpcodeToBitNumber(LDC1) | OpcodeToBitNumber(SWC1) |
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 314 void Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
|
| /art/disassembler/ |
| disassembler_mips.cc | 332 { kITypeMask, 57u << kOpcodeShift, "swc1", "tO", },
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 181 0xef 0xde 0x06 0xe7 # CHECK: swc1 $f6, -8465($24)
|
