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  /external/llvm/test/CodeGen/Hexagon/
NVJumpCmp.ll 87 !5 = !{!"llvm.loop.vectorize.width", i32 1}
  /external/llvm/test/Feature/
optnone-opt.ll 5 ; RUN: opt -bb-vectorize -dce -die -loweratomic -S -debug %s 2>&1 | FileCheck %s --check-prefix=OPT-MORE
  /external/llvm/test/Transforms/LoopVectorize/PowerPC/
large-loop-rdx.ll 1 ; RUN: opt < %s -loop-vectorize -S | FileCheck %s
  /external/llvm/test/Transforms/LoopVectorize/X86/
assume.ll 1 ; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7 -S | FileCheck %s
illegal-parallel-loop-uniform-write.ll 1 ; RUN: opt < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s
unroll_selection.ll 1 ; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -force-vector-width=4 -force-vector-interleave=0 -dce -S | FileCheck %s
parallel-loops.ll 1 ; RUN: opt < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s
vector_ptr_load_store.ll 1 ; RUN: opt -basicaa -loop-vectorize -mcpu=corei7-avx -debug -S < %s 2>&1 | FileCheck %s
  /external/llvm/test/Transforms/LoopVectorize/
bzip_reverse_loops.ll 1 ; RUN: opt < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S -enable-if-conversion | FileCheck %s
flags.ll 1 ; RUN: opt < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s
no_int_induction.ll 1 ; RUN: opt < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s
ptr_loops.ll 1 ; RUN: opt < %s -basicaa -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S -enable-if-conversion | FileCheck %s
debugloc.ll 1 ; RUN: opt -S < %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s
incorrect-dom-info.ll 3 ; RUN: opt < %s -loop-vectorize -verify-dom-info
reverse_induction.ll 1 ; RUN: opt < %s -loop-vectorize -force-vector-interleave=2 -force-vector-width=4 -S | FileCheck %s
runtime-check-readonly-address-space.ll 1 ; RUN: opt -S -march=r600 -mcpu=cayman -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s
  /external/llvm/test/Transforms/SLPVectorizer/ARM/
sroa.ll 7 ; Code like this is the result of SROA. Make sure we don't vectorize this
  /external/llvm/test/Transforms/SLPVectorizer/X86/
commutativity.ll 5 ; to vectorize this case
ordering.ll 44 ; Make sure we don't vectorize these phis - they have invokes as inputs.
  /external/llvm/tools/opt/
opt.cpp 232 // This is final, unless there is a #pragma vectorize enable
235 // If option wasn't forced via cmd line (-vectorize-loops, -loop-vectorize)
239 // When #pragma vectorize is on for SLP, do the same as above
  /external/eigen/Eigen/src/Core/
Redux.h 238 else // too small to vectorize anything.
279 else // too small to vectorize anything.
  /external/skia/src/core/
SkConvolver.cpp 160 // There's a bug somewhere here with GCC autovectorization (-ftree-vectorize). We originally
164 // Dropping to -O2 disables -ftree-vectorize. GCC 4.6 needs noinline. https://bug.skia.org/2575
  /external/llvm/include/llvm/
LinkAllPasses.h 44 #include "llvm/Transforms/Vectorize.h"
  /external/llvm/test/Transforms/BBVectorize/X86/
pr15289.ll 1 ; RUN: opt < %s -basicaa -bb-vectorize -disable-output
  /external/llvm/include/llvm/Analysis/
LoopAccessAnalysis.h 229 /// \brief The maximum number of bytes of a vector register we can vectorize
234 /// vectorize the loop with a dynamic array access check.
290 /// vectorize this loop with runtime checks.

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