| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
| and.d | 71 f4: 00 fd 00 60 6000fd00 and.f r0,r1,0x200
73 fc: 00 05 1f 60 601f0500 and.f r0,0x200,r2
82 120: 0c fd 00 60 6000fd0c and.le.f r0,r1,0x200
84 128: 0a 05 1f 60 601f050a and.ge.f r0,0x200,r2
|
| bic.d | 71 f4: 00 fd 00 70 7000fd00 bic.f r0,r1,0x200
73 fc: 00 05 1f 70 701f0500 bic.f r0,0x200,r2
82 120: 0c fd 00 70 7000fd0c bic.le.f r0,r1,0x200
84 128: 0a 05 1f 70 701f050a bic.ge.f r0,0x200,r2
|
| or.d | 71 f4: 00 fd 00 68 6800fd00 or.f r0,r1,0x200
73 fc: 00 05 1f 68 681f0500 or.f r0,0x200,r2
82 120: 0c fd 00 68 6800fd0c or.le.f r0,r1,0x200
84 128: 0a 05 1f 68 681f050a or.ge.f r0,0x200,r2
|
| sbc.d | 71 f4: 00 fd 00 58 5800fd00 sbc.f r0,r1,0x200
73 fc: 00 05 1f 58 581f0500 sbc.f r0,0x200,r2
82 120: 0c fd 00 58 5800fd0c sbc.le.f r0,r1,0x200
84 128: 0a 05 1f 58 581f050a sbc.ge.f r0,0x200,r2
|
| sub.d | 71 f4: 00 fd 00 50 5000fd00 sub.f r0,r1,0x200
73 fc: 00 05 1f 50 501f0500 sub.f r0,0x200,r2
82 120: 0c fd 00 50 5000fd0c sub.le.f r0,r1,0x200
84 128: 0a 05 1f 50 501f050a sub.ge.f r0,0x200,r2
|
| xor.d | 71 f4: 00 fd 00 78 7800fd00 xor.f r0,r1,0x200
73 fc: 00 05 1f 78 781f0500 xor.f r0,0x200,r2
82 120: 0c fd 00 78 7800fd0c xor.le.f r0,r1,0x200
84 128: 0a 05 1f 78 781f050a xor.ge.f r0,0x200,r2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/msp430/ |
| opcode.s | 57 add &0x200, &0x172
|
| /toolchain/binutils/binutils-2.25/include/coff/ |
| aux-coff.h | 30 #define STYP_LIB 0x200
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-scripts/ |
| overlay-size.t | 41 . += 0x200;
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-evex-lig256-intel.d | 33 [ ]*[a-f0-9]+: 62 61 16 27 58 b2 00 02 00 00 vaddss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
34 [ ]*[a-f0-9]+: 62 61 16 27 58 72 80 vaddss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
[all...] |
| x86-64-evex-lig512-intel.d | 33 [ ]*[a-f0-9]+: 62 61 16 47 58 b2 00 02 00 00 vaddss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
34 [ ]*[a-f0-9]+: 62 61 16 47 58 72 80 vaddss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
[all...] |
| avx512f_vl-wig1-intel.d | 17 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
18 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
41 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 00 02 00 00[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx\+0x200\]
42 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 80[ ]*vpmovsxbq ymm6\{k7\},DWORD PTR \[edx-0x200\]
65 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 00 02 00 00[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx\+0x200\]
66 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 80[ ]*vpmovsxwq xmm6\{k7\},DWORD PTR \[edx-0x200\]
81 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 00 02 00 00[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx\+0x200\]
82 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 80[ ]*vpmovzxbd xmm6\{k7\},DWORD PTR \[edx-0x200\]
105 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 00 02 00 00[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx\+0x200\]
106 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 80[ ]*vpmovzxbq ymm6\{k7\},DWORD PTR \[edx-0x200\]
[all...] |
| avx512f_vl-wig1.d | 17 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%edx\),%xmm6\{%k7\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 21 72 80[ ]*vpmovsxbd -0x200\(%edx\),%xmm6\{%k7\}
41 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 b2 00 02 00 00[ ]*vpmovsxbq 0x200\(%edx\),%ymm6\{%k7\}
42 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 22 72 80[ ]*vpmovsxbq -0x200\(%edx\),%ymm6\{%k7\}
65 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 b2 00 02 00 00[ ]*vpmovsxwq 0x200\(%edx\),%xmm6\{%k7\}
66 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 24 72 80[ ]*vpmovsxwq -0x200\(%edx\),%xmm6\{%k7\}
81 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 b2 00 02 00 00[ ]*vpmovzxbd 0x200\(%edx\),%xmm6\{%k7\}
82 [ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 31 72 80[ ]*vpmovzxbd -0x200\(%edx\),%xmm6\{%k7\}
105 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 b2 00 02 00 00[ ]*vpmovzxbq 0x200\(%edx\),%ymm6\{%k7\}
106 [ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 32 72 80[ ]*vpmovzxbq -0x200\(%edx\),%ymm6\{%k7\
[all...] |
| x86-64-avx512f_vl-wig1-intel.d | 18 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx\+0x200\]
19 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd xmm30,DWORD PTR \[rdx-0x200\]
45 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 00 02 00 00[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx\+0x200\]
46 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 80[ ]*vpmovsxbq ymm30,DWORD PTR \[rdx-0x200\]
72 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 00 02 00 00[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx\+0x200\]
73 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 80[ ]*vpmovsxwq xmm30,DWORD PTR \[rdx-0x200\]
90 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 00 02 00 00[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx\+0x200\]
91 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 80[ ]*vpmovzxbd xmm30,DWORD PTR \[rdx-0x200\]
117 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 00 02 00 00[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx\+0x200\]
118 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 80[ ]*vpmovzxbq ymm30,DWORD PTR \[rdx-0x200\]
[all...] |
| x86-64-avx512f_vl-wig1.d | 18 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 b2 00 02 00 00[ ]*vpmovsxbd 0x200\(%rdx\),%xmm30
19 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 21 72 80[ ]*vpmovsxbd -0x200\(%rdx\),%xmm30
45 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 b2 00 02 00 00[ ]*vpmovsxbq 0x200\(%rdx\),%ymm30
46 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 22 72 80[ ]*vpmovsxbq -0x200\(%rdx\),%ymm30
72 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 b2 00 02 00 00[ ]*vpmovsxwq 0x200\(%rdx\),%xmm30
73 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 24 72 80[ ]*vpmovsxwq -0x200\(%rdx\),%xmm30
90 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 b2 00 02 00 00[ ]*vpmovzxbd 0x200\(%rdx\),%xmm30
91 [ ]*[a-f0-9]+:[ ]*62 62 fd 08 31 72 80[ ]*vpmovzxbd -0x200\(%rdx\),%xmm30
117 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 b2 00 02 00 00[ ]*vpmovzxbq 0x200\(%rdx\),%ymm30
118 [ ]*[a-f0-9]+:[ ]*62 62 fd 28 32 72 80[ ]*vpmovzxbq -0x200\(%rdx\),%ymm3
[all...] |
| evex-lig256.d | 33 [ ]*[a-f0-9]+: 62 f1 56 2f 58 b2 00 02 00 00 vaddss 0x200\(%edx\),%xmm5,%xmm6\{%k7\}
34 [ ]*[a-f0-9]+: 62 f1 56 2f 58 72 80 vaddss -0x200\(%edx\),%xmm5,%xmm6\{%k7\}
[all...] |
| evex-lig512.d | 33 [ ]*[a-f0-9]+: 62 f1 56 4f 58 b2 00 02 00 00 vaddss 0x200\(%edx\),%xmm5,%xmm6\{%k7\}
34 [ ]*[a-f0-9]+: 62 f1 56 4f 58 72 80 vaddss -0x200\(%edx\),%xmm5,%xmm6\{%k7\}
[all...] |
| x86-64-avx512f-intel.d | 45 [ ]*[a-f0-9]+: 62 61 14 50 58 b2 00 02 00 00 vaddps zmm30,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\}
46 [ ]*[a-f0-9]+: 62 61 14 50 58 72 80 vaddps zmm30,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\}
69 [ ]*[a-f0-9]+: 62 61 16 07 58 b2 00 02 00 00 vaddss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
70 [ ]*[a-f0-9]+: 62 61 16 07 58 72 80 vaddss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
84 [ ]*[a-f0-9]+: 62 63 15 50 03 b2 00 02 00 00 7b valignd zmm30,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\},0x7b
85 [ ]*[a-f0-9]+: 62 63 15 50 03 72 80 7b valignd zmm30,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\},0x7b
112 [ ]*[a-f0-9]+: 62 62 15 50 65 b2 00 02 00 00 vblendmps zmm30,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\}
113 [ ]*[a-f0-9]+: 62 62 15 50 65 72 80 vblendmps zmm30,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\}
162 [ ]*[a-f0-9]+: 62 62 7d 48 18 b2 00 02 00 00 vbroadcastss zmm30,DWORD PTR \[rdx\+0x200\]
163 [ ]*[a-f0-9]+: 62 62 7d 48 18 72 80 vbroadcastss zmm30,DWORD PTR \[rdx-0x200\]
[all...] |
| avx512f-intel.d | 45 [ ]*[a-f0-9]+: 62 f1 54 58 58 b2 00 02 00 00 vaddps zmm6,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\}
46 [ ]*[a-f0-9]+: 62 f1 54 58 58 72 80 vaddps zmm6,zmm5,DWORD PTR \[edx-0x200\]\{1to16\}
69 [ ]*[a-f0-9]+: 62 f1 56 0f 58 b2 00 02 00 00 vaddss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\]
70 [ ]*[a-f0-9]+: 62 f1 56 0f 58 72 80 vaddss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\]
84 [ ]*[a-f0-9]+: 62 f3 55 58 03 b2 00 02 00 00 7b valignd zmm6,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\},0x7b
85 [ ]*[a-f0-9]+: 62 f3 55 58 03 72 80 7b valignd zmm6,zmm5,DWORD PTR \[edx-0x200\]\{1to16\},0x7b
112 [ ]*[a-f0-9]+: 62 f2 55 58 65 b2 00 02 00 00 vblendmps zmm6,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\}
113 [ ]*[a-f0-9]+: 62 f2 55 58 65 72 80 vblendmps zmm6,zmm5,DWORD PTR \[edx-0x200\]\{1to16\}
162 [ ]*[a-f0-9]+: 62 f2 7d 48 18 b2 00 02 00 00 vbroadcastss zmm6,DWORD PTR \[edx\+0x200\]
163 [ ]*[a-f0-9]+: 62 f2 7d 48 18 72 80 vbroadcastss zmm6,DWORD PTR \[edx-0x200\]
[all...] |
| x86-64-evex-lig256.d | 33 [ ]*[a-f0-9]+: 62 61 16 27 58 b2 00 02 00 00 vaddss 0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
34 [ ]*[a-f0-9]+: 62 61 16 27 58 72 80 vaddss -0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
[all...] |
| x86-64-evex-lig512.d | 33 [ ]*[a-f0-9]+: 62 61 16 47 58 b2 00 02 00 00 vaddss 0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
34 [ ]*[a-f0-9]+: 62 61 16 47 58 72 80 vaddss -0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
[all...] |
| /external/v8/test/mjsunit/tools/ |
| codemap.js | 101 codeMap.addCode(0x1500, newCodeEntry(0x200, 'code1'));
109 assertEntry(codeMap, 'code1', 0x1500 + 0x200 - 1);
127 codeMap.addCode(0x1500, newCodeEntry(0x200, 'code1'));
144 codeMap.addCode(0x1500, newCodeEntry(0x200, 'code'));
168 codeMap.addCode(0x1500, newCodeEntry(0x200, 'code1'));
|
| /external/zlib/src/contrib/minizip/ |
| iowin32.c | 110 WCHAR filenameW[FILENAME_MAX + 0x200 + 1];
111 MultiByteToWideChar(CP_ACP,0,(const char*)filename,-1,filenameW,FILENAME_MAX + 0x200);
135 WCHAR filenameW[FILENAME_MAX + 0x200 + 1];
136 MultiByteToWideChar(CP_ACP,0,(const char*)filename,-1,filenameW,FILENAME_MAX + 0x200);
183 WCHAR filenameW[FILENAME_MAX + 0x200 + 1];
184 MultiByteToWideChar(CP_ACP,0,(const char*)filename,-1,filenameW,FILENAME_MAX + 0x200);
|
| /bionic/libc/kernel/uapi/asm-x86/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /bionic/libc/kernel/uapi/linux/ |
| qnx4_fs.h | 40 #define QNX4_BLOCK_SIZE 0x200
45 #define QNX4_XBLK_ENTRY_SIZE 0x200
|
