| /external/llvm/lib/IR/ |
| Verifier.cpp | [all...] |
| /external/clang/lib/Sema/ |
| SemaDeclAttr.cpp | [all...] |
| SemaExprCXX.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 774 unsigned Align = Flags.getByValAlign();
776 int FI = MFI->CreateStackObject(Size, Align, false);
780 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
[all...] |
| /external/clang/lib/Frontend/Rewrite/ |
| RewriteModernObjC.cpp | [all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 579 // [rn {:align}] Offset
580 // [rn {:align}]! PostIndex
581 explicit NeonMemOperand(Register rn, AddrMode am = Offset, int align = 0);
583 // [rn {:align}], rm PostIndex
584 explicit NeonMemOperand(Register rn, Register rm, int align = 0);
588 int align() const { return align_; }
591 void SetAlignment(int align);
734 // possible to align the pc offset to a multiple
736 void Align(int m);
737 // Insert the smallest number of zero bytes possible to align the pc offse
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.h | 774 // possible to align the pc offset to a multiple
776 void Align(int m);
777 // Insert the smallest number of zero bytes possible to align the pc offset
[all...] |
| assembler-arm64.cc | 387 // 3) align the pool entries to 64-bit.
410 assm_->Align(8);
597 void Assembler::Align(int m) {
[all...] |
| /external/v8/src/full-codegen/ |
| full-codegen.cc | 82 masm()->Align(kPointerSize);
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | 551 // possible to align the pc offset to a multiple
553 void Align(int m);
554 // Insert the smallest number of zero bytes possible to align the pc offset
841 void align(Register rd, Register rs, Register rt, uint8_t bp);
[all...] |
| assembler-mips.cc | 303 void Assembler::Align(int m) {
318 Align(4);
2070 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 555 // possible to align the pc offset to a multiple
557 void Align(int m);
558 // Insert the smallest number of zero bytes possible to align the pc offset
[all...] |
| assembler-mips64.cc | 280 void Assembler::Align(int m) {
292 Align(4);
2466 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/ppc/ |
| assembler-ppc.h | 559 // possible to align the pc offset to a multiple
561 void Align(int m);
562 // Insert the smallest number of zero bytes possible to align the pc offset
[all...] |
| assembler-ppc.cc | 233 void Assembler::Align(int m) {
242 void Assembler::CodeTargetAlign() { Align(8); }
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/skia/tools/debugger/ |
| SkDrawCommand.cpp | [all...] |
| /external/v8/src/x64/ |
| assembler-x64.cc | 299 void Assembler::Align(int m) {
307 Align(16); // Preferred alignment of jump targets on x64.
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | 423 sub r4, sp, r4 @ reserve & align *stack* to 16 bytes: native calling
479 and r7, #0xFFFFFFF0 @ Align stack pointer
[all...] |
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | 364 srl $t0, $t0, 4 # Align stack pointer to 16 bytes
653 subu $t0, $sp, $t0 # reserve & align *stack* to 16 bytes:
779 subu $t0, $sp, $t0 # reserve & align *stack* to 16 bytes:
[all...] |
| /external/skia/src/core/ |
| SkDraw.cpp | [all...] |
