| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 186 ENTRY(R15)
204 ENTRY(R15)
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| sys_linux_arm.s | 396 MOVW $0xffff0fc0, R15 // R15 is hardware PC.
432 MOVW $0xffff0fa0, R15 // R15 is hardware PC.
|
| sys_netbsd_amd64.s | 220 MOVQ R15, DI // Load address of ucontext
|
| /prebuilts/go/linux-x86/src/runtime/ |
| sys_linux_arm.s | 396 MOVW $0xffff0fc0, R15 // R15 is hardware PC.
432 MOVW $0xffff0fa0, R15 // R15 is hardware PC.
|
| sys_netbsd_amd64.s | 220 MOVQ R15, DI // Load address of ucontext
|
| /art/compiler/utils/arm/ |
| assembler_arm32_test.cc | 78 new arm::Register(arm::R15)
98 new arm::Register(arm::R15)
176 if (*reg == arm::R15) { // Skip PC.
258 return arm::R15;
|
| managed_register_arm_test.cc | 57 reg = ArmManagedRegister::FromCoreRegister(R15);
64 EXPECT_EQ(R15, reg.AsCoreRegister());
[all...] |
| /external/llvm/include/llvm/DebugInfo/PDB/ |
| PDBTypes.h | 419 R15 = 343,
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/ |
| sh2a-nofpu.s | 46 movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
47 movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
48 movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
49 movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
|
| sh2a.s | [all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/ |
| sh2a-nofpu.s | 46 movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
47 movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
48 movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
49 movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
|
| sh2a.s | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 734 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
|
| X86AsmBackend.cpp | 485 case X86::R15:
562 // pushq %r15
570 // .cfi_offset %r15, -24
662 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
|
| /external/valgrind/coregrind/m_sigframe/ |
| sigframe-amd64-linux.c | 352 SC2(r15,R15);
552 tst->arch.vex.guest_R15 = sc->r15;
|
| /external/boringssl/src/ssl/test/runner/poly1305/ |
| poly1305_amd64.s | 27 MOVQ R15,64(SP)
493 MOVQ 64(SP),R15
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 167 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
178 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
|
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | 160 registers_.push_back(new x86_64::CpuRegister(x86_64::R15));
177 secondary_register_names_.emplace(x86_64::CpuRegister(x86_64::R15), "r15d");
194 tertiary_register_names_.emplace(x86_64::CpuRegister(x86_64::R15), "r15w");
211 quaternary_register_names_.emplace(x86_64::CpuRegister(x86_64::R15), "r15b");
[all...] |
| /external/libunwind/src/ptrace/ |
| _UPT_reg_offset.c | 308 UNW_R_OFF(R15, r15)
|
| /external/llvm/lib/DebugInfo/PDB/ |
| PDBExtras.cpp | 142 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_RegisterId, R15, OS)
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 526 case Hexagon::R15:
|
| HexagonMCCodeEmitter.cpp | 103 Hexagon::R14, Hexagon::R15};
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 407 case X86::R15: return X86::R15D;
|
| /external/llvm/test/MC/X86/ |
| intel-syntax.s | 74 // CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
75 vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
|
| /external/valgrind/VEX/auxprogs/ |
| genoffsets.c | 119 GENOFFSET(AMD64,amd64,R15);
184 GENOFFSET(S390X,s390x,r15);
210 GENOFFSET(MIPS32,mips32,r15);
211 GENOFFSET(MIPS32,mips32,r15);
247 GENOFFSET(MIPS64,mips64,r15);
248 GENOFFSET(MIPS64,mips64,r15);
284 GENOFFSET(TILEGX,tilegx,r15);
|
