| /frameworks/base/packages/Osu/src/com/android/anqp/eap/ |
| Credential.java | 14 Reserved,
40 CredType.Reserved;
|
| NonEAPInnerAuth.java | 16 public enum NonEAPType {Reserved, PAP, CHAP, MSCHAP, MSCHAPv2}
41 NonEAPType.Reserved;
|
| /frameworks/opt/net/wifi/service/java/com/android/server/wifi/anqp/eap/ |
| Credential.java | 14 Reserved,
40 CredType.Reserved;
|
| NonEAPInnerAuth.java | 16 public enum NonEAPType {Reserved, PAP, CHAP, MSCHAP, MSCHAPv2}
41 NonEAPType.Reserved;
|
| /frameworks/opt/net/wifi/service/java/com/android/server/wifi/anqp/ |
| VenueNameElement.java | 33 mGroup = VenueGroup.Reserved;
34 mType = VenueType.Reserved;
39 mType = VenueType.Reserved;
85 Reserved
167 Reserved
|
| IPAddressTypeAvailabilityElement.java | 15 public enum IPv6Availability {NotAvailable, Available, Unknown, Reserved}
|
| NetworkAuthenticationTypeElement.java | 24 Reserved
64 NwkAuthTypeEnum.Reserved :
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| af_irda.h | 118 u_char Reserved[2];
181 u_char Reserved[3];
187 u_char Reserved[2];
202 u_char Reserved[3];
208 u_char Reserved[2];
|
| usb200.h | 51 UCHAR Reserved:3;
99 USHORT Reserved:3;
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 47 BitVector Reserved(getNumRegs());
50 Reserved.set(Reg);
51 return Reserved;
|
| /external/freetype/src/sfnt/ |
| ttmtx.c | 135 FT_FRAME_SHORT ( Reserved[0] ),
136 FT_FRAME_SHORT ( Reserved[1] ),
137 FT_FRAME_SHORT ( Reserved[2] ),
138 FT_FRAME_SHORT ( Reserved[3] ),
|
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 12 // reserved registers depend on calling conventions and other dynamic
64 // Different reserved registers?
66 if (Reserved.size() != RR.size() || RR != Reserved) {
68 Reserved = RR;
76 /// compute - Compute the preferred allocation order for RC with reserved
83 // Raw register count, including all reserved regs.
100 // Remove reserved registers from the allocation order.
101 if (Reserved.test(PhysReg))
154 /// nonoverlapping reserved registers. However, computing the allocation orde
[all...] |
| /external/pdfium/third_party/freetype/src/sfnt/ |
| ttmtx.c | 135 FT_FRAME_SHORT ( Reserved[0] ),
136 FT_FRAME_SHORT ( Reserved[1] ),
137 FT_FRAME_SHORT ( Reserved[2] ),
138 FT_FRAME_SHORT ( Reserved[3] ),
|
| /external/icu/icu4c/source/test/perf/unisetperf/draft/ |
| contperf.bat | 2 rem others. All Rights Reserved.
|
| span16perf.bat | 2 rem others. All Rights Reserved.
|
| span8perf.bat | 2 rem others. All Rights Reserved.
|
| /external/icu/icu4c/source/test/perf/utrie2perf/ |
| utrie2perf.bat | 2 rem All Rights Reserved.
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ddk/ |
| drmk.h | 20 ULONG Reserved;
58 IN PVOID Reserved,
|
| mce.h | 8 ULONG Reserved;
181 UCHAR Reserved;
206 UCHAR Reserved:7;
226 UCHAR Reserved:4;
235 UCHAR Reserved;
247 USHORT lid = (USHORT)((UCHAR)(section->Reserved));
249 lid |= (USHORT)((UCHAR)(Log->TimeStamp.s.Reserved) << 8);
251 lid |= (USHORT)((UCHAR)(Log->TimeStamp.Reserved) << 8);
267 ULONGLONG Reserved:59;
579 ULONGLONG Reserved:39
649 ULONGLONG reserved:16; member in struct:_PROCESSOR_LOCAL_ID::__anon40837
[all...] |
| scsi.h | 747 UCHAR Reserved:4;
[all...] |
| strmini.h | 66 ULONG Reserved;
79 ULONG Reserved[2];
100 ULONG Reserved[2];
132 ULONG Reserved[2];
145 ULONG Reserved[2];
270 ULONG Reserved[1];
286 ULONG Reserved;
307 ULONG Reserved[1];
375 ULONG Reserved[2];
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| got-dump-1.d | 10 Reserved entries:
|
| got-dump-2.d | 10 Reserved entries:
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 119 // On PPC64, we might need to save r2 (but only if it is not reserved).
166 BitVector Reserved(getNumRegs());
172 Reserved.set(PPC::ZERO);
173 Reserved.set(PPC::ZERO8);
177 Reserved.set(PPC::FP);
178 Reserved.set(PPC::FP8);
182 Reserved.set(PPC::BP);
183 Reserved.set(PPC::BP8);
185 // The counter registers must be reserved so that counter-based loops can
187 Reserved.set(PPC::CTR)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 28 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
32 Reserved.set(*R);
45 // 98/99 need to be reserved for flat_scr, and 100/101 for vcc. This is the
70 BitVector Reserved(getNumRegs());
71 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
74 // this seems likely to result in bugs, so I'm marking them as reserved.
75 reserveRegisterTuples(Reserved, AMDGPU::EXEC);
76 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
80 reserveRegisterTuples(Reserved, AMDGPU::SGPR102_SGPR103);
87 reserveRegisterTuples(Reserved, AMDGPU::SGPR98_SGPR99)
[all...] |
