| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| unwind-bad.s | 66 .spillreg.p p1, f16, f0
|
| unwind-ok.s | 42 .restorereg f16
100 .spillreg.p p63, f16, f32
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 12 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1.s | 15 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| dual03.d | 53 8c: 30 f0 f0 4b fadd.ss %f30,%f31,%f16
|
| fldst01.s | 40 fld.l -4(%r14)++,%f16
|
| fldst04.s | 40 fst.l %f16,-4(%r14)++
|
| fldst07.s | 40 pfld.l -4(%r14)++,%f16
|
| fldst01.d | 43 84: ff ff d0 25 fld.l -4\(%r14\)\+\+,%f16
|
| fldst04.d | 43 84: ff ff d0 2d fst.l %f16,-4\(%r14\)\+\+
|
| fldst07.d | 43 84: ff ff d0 65 pfld.l -4\(%r14\)\+\+,%f16
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 50 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
53 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/ |
| all-opcodes.d | [all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 7 abs.s $f9,$f16
41 c.ngle.d $f0,$f16
50 cvt.d.l $f4,$f16
134 lwc1 $f16,10225($k0)
153 mul.d $f20,$f20,$f16
|
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_rtl_ppc64.S | 70 stfd f16,192(r3)
215 stfd f16,192(r3)
|
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 421 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
441 if (OpVT == MVT::f16) {
460 if (RetVT == MVT::f16) {
[all...] |
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 27 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 31 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| set-arch.d | 99 0000016c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16
100 00000170 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18
115 000001ac <[^>]*> 46d283ad plu\.ps \$f14,\$f16,\$f18
116 000001b0 <[^>]*> 46d4942e pul\.ps \$f16,\$f18,\$f20
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| power6.d | 23 34: (ee 11 90 04|04 90 11 ee) dadd f16,f17,f18
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| cortex-a8-fix-b-rel-arm.d | 16 8f16: f000 b87b b\.w 9010 <__targetfn_from_thumb>
|
| cortex-a8-fix-bl-rel-arm.d | 16 8f16: f7ff eff4 blx 8f00 <targetfn>
|
| cortex-a8-fix-bl-rel-thumb.d | 17 8f16: f7ff fff3 bl 8f00 <targetfn>
|
| cortex-a8-fix-blx-rel-arm.d | 16 8f16: f7ff eff4 blx 8f00 <targetfn>
|
| cortex-a8-fix-blx-rel-thumb.d | 17 8f16: f7ff fff3 bl 8f00 <targetfn>
|
