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  /dalvik/dx/tests/005-cp-top-down/
small-class.txt 18 0b 0011 000b # 0008: ifaceMethod[Small.blort:()V]
19 0a 0011 000b # 0009: method[Small.blort:()V]
20 09 0011 000c # 000a: field[Small.blort:x/y/Zzz]
27 07 0013 # 0011: class[Small]
32 0011 # this_class
expected.txt 23 0011: type{Small}
  /external/opencv3/3rdparty/libtiff/
t4.h 59 { 8, 0x35, 0 }, /* 0011 0101 */
69 { 5, 0x7, 10 }, /* 0011 1 */
87 { 7, 0x18, 28 }, /* 0011 000 */
89 { 8, 0x3, 30 }, /* 0000 0011 */
93 { 8, 0x13, 34 }, /* 0001 0011 */
109 { 8, 0x53, 50 }, /* 0101 0011 */
120 { 8, 0x32, 61 }, /* 0011 0010 */
121 { 8, 0x33, 62 }, /* 0011 0011 */
122 { 8, 0x34, 63 }, /* 0011 0100 *
    [all...]
  /external/pdfium/third_party/libtiff/
t4.h 59 { 8, 0x35, 0 }, /* 0011 0101 */
69 { 5, 0x7, 10 }, /* 0011 1 */
87 { 7, 0x18, 28 }, /* 0011 000 */
89 { 8, 0x3, 30 }, /* 0000 0011 */
93 { 8, 0x13, 34 }, /* 0001 0011 */
109 { 8, 0x53, 50 }, /* 0101 0011 */
120 { 8, 0x32, 61 }, /* 0011 0010 */
121 { 8, 0x33, 62 }, /* 0011 0011 */
122 { 8, 0x34, 63 }, /* 0011 0100 *
    [all...]
  /dalvik/dx/tests/046-dex-exceptions/
expected.txt 32 0011: return v0
37 0016: goto 0011 // -0005
42 001b: goto 0011 // -000a
  /external/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.h 618 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
619 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
620 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
630 TRCSTATR = 0x8818, // 10 001 0000 0011 000
634 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
653 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
699 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
709 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
725 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
741 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 11
    [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
z8kgen.c 42 {"------", 2, 8, "0011 0110 0000 0000", "bpt", 0}, /* Breakpoint used by the simulator. */
51 {"------", 10, 8, "0011 0110 imm8", "rsvd36", 0},
52 {"------", 10, 8, "0011 1000 imm8", "rsvd38", 0},
216 {"------", 10, 16, "0011 1101 ssss dddd", "in rd,@ri", 0},
217 {"------", 12, 8, "0011 1100 ssss dddd", "inb rbd,@ri", 0},
218 {"------", 12, 16, "0011 1011 dddd 0100 imm16", "in rd,imm16", 0},
219 {"------", 10, 8, "0011 1010 dddd 0100 imm16", "inb rbd,imm16", 0},
228 {"---V--", 21, 16, "0011 1011 ssss 1000 0000 aaaa ddN0 1000", "ind @rd,@ri,ra", 0},
229 {"---V--", 21, 8, "0011 1010 ssss 1000 0000 aaaa ddN0 1000", "indb @rd,@ri,ra", 0},
230 {"---V--", 11, 16, "0011 1011 ssss 1000 0000 aaaa ddN0 0000", "indr @rd,@ri,ra", 0}
    [all...]
rl78-decode.opc 338 /** 0110 0001 1100 0011 bh $%a0 */
341 /** 0110 0001 1101 0011 bnh $%a0 */
352 /** 0011 0001 1bit 0101 bf %e1, $%a0 */
355 /** 0011 0001 0bit 0101 bf %1, $%a0 */
358 /** 0011 0001 1bit 0100 bf %s1, $%a0 */
361 /** 0011 0001 0bit 0100 bf %s1, $%a0 */
391 /** 0011 0001 1bit 0011 bt %e1, $%a0 */
394 /** 0011 0001 0bit 0011 bt %1, $%a0 *
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/
sh2a-nofpu.s 18 mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
19 mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
22 mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
23 mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
26 mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
27 mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
30 bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
32 bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
34 bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N}, (…)
    [all...]
sh2a.s 15 fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
16 fmov.d @(2048,r5),xd2 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */ {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}
17 fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
18 fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
22 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
23 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
24 addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
40 cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_s (…)
    [all...]
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/
sh2a-nofpu.s 18 mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
19 mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
22 mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
23 mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
26 mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
27 mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
30 bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
32 bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
34 bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N}, (…)
    [all...]
sh2a.s 15 fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
16 fmov.d @(2048,r5),xd2 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */ {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}
17 fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
18 fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
22 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
23 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
24 addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
40 cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_s (…)
    [all...]
  /cts/tests/tests/media/res/raw/
vp90_2_10_show_existing_frame2_vp9_md5 11 c979e2f084760775a567f60f79f28198 -352x288-0011.i420
vp90_2_19_skip_02_vp9_md5 11 57d4952e50ba519388ce7efca7ee505b vp90-2-19-skip-02.webm-208x144-0011.i420
vp90_2_20_big_superframe_01_vp9_md5 11 20b072932f592e67d92cb67b224620b1 vp90-2-20-big_superframe-01.webm-352x288-0011.i420
  /dalvik/dx/tests/002-minimal-valid/
small-class.txt 39 0000 0011 # length
  /dalvik/dx/tests/021-code-attrib-LineNumberTable/
small-class.txt 48 0000 0011 # offset 0000, line #17
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
white.l 10 7 0011 FFE0 jmp \* % eax
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
micromips@mips32r2-sync.d 16 [0-9a-f]+ <[^>]*> 0011 6b7c sync_acquire
25 [0-9a-f]+ <[^>]*> 0011 6b7c sync_acquire
  /dalvik/dx/tests/067-dex-switch-and-try/
expected.txt 16 0011: nop // spacer
61 0011: move-object v2, v3
88 0011: move-object v2, v3
  /prebuilts/go/darwin-x86/src/crypto/tls/
prf_test.go 19 {"0011", "00", "11"},
20 {"001122", "0011", "1122"},
21 {"00112233", "0011", "2233"},
  /prebuilts/go/linux-x86/src/crypto/tls/
prf_test.go 19 {"0011", "00", "11"},
20 {"001122", "0011", "1122"},
21 {"00112233", "0011", "2233"},
  /dalvik/dx/tests/014-field-attrib-ConstantValue/
small-class.txt 29 04 bffeb852 # 0011: float[-1.99]
87 0011 # value
  /dalvik/dx/tests/045-dex-switch-ops/
expected.txt 18 0011: goto 0008 // -0009
45 0011: goto 0008 // -0009
  /dalvik/dx/tests/054-dex-high16/
expected.txt 10 0011: invoke-static {v0, v1}, Blort.sink:(D)V
23 0011: invoke-static {v0}, Blort.sink:(F)V
36 0011: invoke-static {v0}, Blort.sink:(I)V
57 0011: invoke-static {v0, v1}, Blort.sink:(J)V

Completed in 347 milliseconds

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