| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| fix-rm7000-2.s | 5 dmultu $5,$7
10 dmultu $5,$7
15 dmultu $5,$7
19 dmultu $5,$7
21 dmultu $5,$7
25 dmultu $5,$7
|
| micromips@fix-rm7000-2.d | 10 0+0002 <[^>]*> dmultu a1,a3
15 0+0014 <[^>]*> dmultu a1,a3
20 0+0026 <[^>]*> dmultu a1,a3
24 0+0036 <[^>]*> dmultu a1,a3
26 0+003e <[^>]*> dmultu a1,a3
30 0+004e <[^>]*> dmultu a1,a3
|
| r6-64-removed.s | 6 dmultu $2,$3
|
| fix-rm7000-2.d | 10 0+0004 <[^>]*> dmultu a1,a3
21 0+0030 <[^>]*> dmultu a1,a3
29 0+0050 <[^>]*> dmultu a1,a3
39 0+0078 <[^>]*> dmultu a1,a3
44 0+008c <[^>]*> dmultu a1,a3
54 0+00b4 <[^>]*> dmultu a1,a3
|
| vr4120-2.s | 42 dmultu $4,$5
43 dmultu $6,$7
81 dmultu $4,$5
97 dmultu $4,$5
105 dmultu $4,$5
129 dmultu $4,$5
|
| vr4120-2.d | 44 .* <[^>]*> dmultu a0,a1
46 .* <[^>]*> dmultu a2,a3
88 .* <[^>]*> dmultu a0,a1
108 .* <[^>]*> dmultu a0,a1
118 .* <[^>]*> dmultu a0,a1
148 .* <[^>]*> dmultu a0,a1
|
| r6-64-removed.l | 6 .*:6: Error: opcode not supported on this processor: .* \(.*\) `dmultu \$2,\$3'
|
| mul-ilocks.d | 62 0+00cc <[^>]*> dmultu a1,a2
75 0+0100 <[^>]*> dmultu a1,a2
|
| mul.d | 70 0+0100 <[^>]*> dmultu a1,a2
86 0+0148 <[^>]*> dmultu a1,a2
|
| vr4130.d | 329 .* dmultu .*
810 .* dmultu .*
|
| loongson-2e.s | 13 dmultu.g $11, $12, $13
|
| loongson-2f.s | 13 dmultu.g $11, $12, $13
|
| mips16.s | 204 dmultu $2,$3
|
| vr4130.s | 318 check2 dmultu
|
| loongson-2e.d | 18 .*: 7d8d581d dmultu.g \$11,\$12,\$13
|
| loongson-2f.d | 18 .*: 718d5813 dmultu.g \$11,\$12,\$13
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3.s | 13 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 17 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 10 DMULT, DMULTU, DSUB, DSUBU,
183 case DMULTU:
185 TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
186 TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
|
| /external/v8/test/cctest/ |
| test-disasm-mips64.cc | 200 COMPARE(dmultu(a0, a1),
201 "0085001d dmultu a0, a1");
204 COMPARE(dmultu(a6, a7),
205 "014b001d dmultu a6, a7");
208 COMPARE(dmultu(v0, v1),
209 "0043001d dmultu v0, v1");
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 24 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 225 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
229 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| mul.ll | 201 ; GP64-NOT-R6: dmultu $5, $7
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 28 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 27 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
