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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
inval-reg.s 38 cmovna %bx,%ecx label
inval-reg.l 91 [ ]*38[ ]+cmovna %bx,%ecx
  /external/valgrind/none/tests/x86/
insn_cmov.def 81 cmovna eflags[0x041,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
82 cmovna eflags[0x041,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
83 cmovna eflags[0x041,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
84 cmovna eflags[0x041,0x041] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
85 cmovna eflags[0x041,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
86 cmovna eflags[0x041,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
87 cmovna eflags[0x041,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
88 cmovna eflags[0x041,0x041] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
273 cmovna eflags[0x041,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
274 cmovna eflags[0x041,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678
    [all...]
  /external/llvm/test/MC/X86/
intel-syntax.s 342 cmovna eax, ebx
  /external/v8/src/ia32/
disasm-ia32.cc 127 /*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
    [all...]
  /external/v8/src/x64/
disasm-x64.cc 262 {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
    [all...]
  /external/v8/src/x87/
disasm-x87.cc 127 /*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
    [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
i386-opc.tbl     [all...]

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