| /external/llvm/test/MC/Mips/ |
| macro-ddivu.s | 6 ddivu $25,$11
8 # CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
12 ddivu $24,$12
14 # CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
18 ddivu $25,$0
20 # CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
24 ddivu $0,$9
26 # CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
30 ddivu $0,$0
32 # CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f
[all...] |
| macro-ddivu-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6-64-removed.s | 4 ddivu $2, $4
|
| vr4120-2.s | 30 ddivu $0,$7,$8
34 ddivu $0,$7,$8
121 ddivu $0,$4,$5
145 ddivu $0,$4,$5
|
| div.s | 35 ddivu $4,$5,2
|
| r6-64-removed.l | 4 .*:4: Error: invalid operands `ddivu \$2,\$4'
|
| vr4120-2.d | 34 .* <[^>]*> ddivu zero,a3,t0
38 .* <[^>]*> ddivu zero,a3,t0
138 .* <[^>]*> ddivu zero,a0,a1
168 .* <[^>]*> ddivu zero,a0,a1
|
| r6-64.s | 8 ddivu $2,$3,$4
|
| mips16-macro.s | 7 ddivu $5,$6,$7
|
| div-ilocks.d | 102 0+0170 <[^>]*> ddivu zero,a1,at
108 0+0188 <[^>]*> ddivu zero,a1,at
|
| r6-64-n32.d | 17 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0
|
| r6-64-n64.d | 17 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0
|
| div.d | 115 0+01a8 <[^>]*> ddivu zero,a1,at
123 0+01c8 <[^>]*> ddivu zero,a1,at
|
| vr4130.d | 357 .* ddivu .*
838 .* ddivu .*
|
| loongson-2e.s | 17 ddivu.g $23, $24, $25
|
| loongson-2f.s | 17 ddivu.g $23, $24, $25
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64muldiv.ll | 44 ; ACC: ddivu $zero, $4, $5
46 ; GPR: ddivu $2, $4, $5
64 ; ACC: ddivu $zero, $4, $5
|
| mips64instrs.ll | 140 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
144 ; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
172 ; ACCMULDIV: ddivu $zero, $4, $5
|
| divrem.ll | 285 ; GPR64: ddivu $2, $4, $5
366 ; ACC64: ddivu $zero, $4, $5
378 ; GPR64-DAG: ddivu $2, $4, $5
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| udiv.ll | 94 ; GP64-NOT-R6: ddivu $zero, $4, $5
98 ; 64R6: ddivu $2, $4, $5
|
| /external/v8/test/cctest/ |
| test-disasm-mips64.cc | 230 COMPARE(ddivu(a0, a1),
231 "0085001f ddivu a0, a1");
232 COMPARE(ddivu(a6, a7),
233 "014b001f ddivu a6, a7");
234 COMPARE(ddivu(v0, v1),
235 "0043001f ddivu v0, v1");
322 COMPARE(ddivu(a0, a1, a2),
323 "00a6209f ddivu a0, a1, a2");
330 COMPARE(ddivu(a5, a6, a7),
331 "014b489f ddivu a5, a6, a7")
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 9 DDIV, DDIVU, DIV, DIVU,
144 case DDIVU:
148 TEST4("ddivu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
151 TEST4("ddivu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
|
| /external/llvm/lib/Target/Mips/ |
| MicroMips64r6InstrInfo.td | 29 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
90 class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
|
| Mips64r6InstrInfo.td | 64 class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
94 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
|
