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  /external/valgrind/none/tests/mips64/
shift_instructions.stdout.exp-mips64r2 0 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
3 drotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4 drotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
5 drotr $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
6 drotr $t2, $t3, 0x1f :: rt 0x257ad5400000000, rs 0x12bd6aa, imm 0x001f
7 drotr $a0, $a1, 0x0f :: rt 0xad54000000000257, rs 0x12bd6aa, imm 0x000f
8 drotr $s0, $s1, 0x03 :: rt 0x4000000000257ad5, rs 0x12bd6aa, imm 0x0003
9 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
10 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001
    [all...]
rotate_swap.c 56 printf("--- DROTR ---\n");
57 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 16);
58 TESTINST_DROTR("drotr", 0xffff0000ffffffff, 16);
59 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 8);
60 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 4);
61 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 5);
62 TESTINST_DROTR("drotr", 0x31415927ffffffff, 10);
63 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 4);
64 TESTINST_DROTR("drotr", 0x2000ffffffffffff, 0);
65 TESTINST_DROTR("drotr", 0xeeeeffffffffffff, 16)
    [all...]
rotate_swap.stdout.exp-mips64r2 1 --- DROTR ---
2 drotr :: in 0x2000ffffffffffff, out 0xffff2000ffffffff, SA 16
3 drotr :: in 0xffff0000ffffffff, out 0xffffffff0000ffff, SA 16
4 drotr :: in 0x2000ffffffffffff, out 0xff2000ffffffffff, SA 8
5 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
6 drotr :: in 0x2000ffffffffffff, out 0xf90007ffffffffff, SA 5
7 drotr :: in 0x31415927ffffffff, out 0xffcc505649ffffff, SA 10
8 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
9 drotr :: in 0x2000ffffffffffff, out 0x2000ffffffffffff, SA 0
10 drotr :: in 0xeeeeffffffffffff, out 0xffffeeeeffffffff, SA 1
    [all...]
shift_instructions.c 6 DROTR=0, DROTR32, DROTRV, DSLL,
18 for (op = DROTR; op <= SRLV; op++) {
21 case DROTR:
24 TEST2("drotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
25 TEST2("drotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
26 TEST2("drotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
27 TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
28 TEST2("drotr $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
29 TEST2("drotr $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
30 TEST2("drotr $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1)
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
mips64r2.s 50 drotr $25, $10, 4 # dror
52 drotr $25, $10, 36 # dror32
54 drotr $25, $10, $4 # drorv
  /external/llvm/test/CodeGen/Mips/
mips64shift.ll 90 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
99 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
  /external/llvm/test/MC/Mips/mips64/
invalid-mips64r2.s 9 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/MC/Mips/
mips_directives.s 76 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
78 drotr $9, $6, 30
rotations64.s 111 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
131 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
136 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
139 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
159 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
164 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
182 # CHECK-64R: drotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x7a]
185 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
190 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
195 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa
    [all...]
mips64-alu-instructions.s 76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
101 drotr $9, $6, 20
  /external/llvm/test/MC/Mips/mips5/
invalid-mips64r2.s 14 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/MC/Mips/mips64r2/
invalid.s 33 drotr $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 6-bit unsigned immediate
34 drotr $2, $3, 64 # CHECK: :[[@LINE]]:23: error: expected 6-bit unsigned immediate
valid.s 96 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
97 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
  /external/v8/test/cctest/
test-disasm-mips64.cc 542 COMPARE(drotr(a0, a1, 0),
543 "0025203a drotr a0, a1, 0");
544 COMPARE(drotr(s0, s1, 8),
545 "0031823a drotr s0, s1, 8");
546 COMPARE(drotr(a6, a7, 24),
547 "002b563a drotr a6, a7, 24");
548 COMPARE(drotr(v0, v1, 31),
549 "002317fa drotr v0, v1, 31");
    [all...]
  /external/llvm/test/MC/Mips/mips64r3/
valid.s 96 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
97 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
  /external/llvm/test/MC/Mips/mips64r5/
valid.s 96 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
97 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
  /external/llvm/test/MC/Disassembler/Mips/mips64r2/
valid-mips64r2-el.txt 125 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
126 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
272 0xba 0xa1 0x3b 0x00 # CHECK: drotr $20, $27, 6
valid-mips64r2.txt 55 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
59 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
62 0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6
  /external/llvm/test/MC/Disassembler/Mips/mips64r3/
valid-mips64r3-el.txt 122 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
123 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
valid-mips64r3.txt 52 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
56 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
59 0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6
  /external/llvm/test/MC/Disassembler/Mips/mips64r5/
valid-mips64r5-el.txt 122 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
123 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
valid-mips64r5.txt 52 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
56 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
59 0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 78 case Mips::DROTR:
163 case Mips::DROTR:
    [all...]
  /external/llvm/lib/Target/Mips/
Mips64InstrInfo.td 159 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
  /art/compiler/utils/mips64/
assembler_mips64.h 174 void Drotr(GpuRegister rd, GpuRegister rt, int shamt);

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