| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
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| /prebuilts/ndk/current/platforms/android-12/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
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| /prebuilts/ndk/current/platforms/android-13/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-14/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-15/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-16/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-17/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-18/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-19/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/current/platforms/android-9/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
|
| processor.h | 49 unsigned int dspcontrol; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /external/valgrind/none/tests/mips32/ |
| mips32_dsp.stdout.exp-BE | 2 absq_s.ph $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0
3 absq_s.ph $t2, $t3 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0
4 absq_s.ph $t4, $t1 :: rd 0x05442435 rt 0xfabc2435 DSPControl 0x0
5 absq_s.ph $t6, $t7 :: rd 0x73467fff rt 0x73468000 DSPControl 0x100000
6 absq_s.ph $t5, $t3 :: rd 0x7fff0000 rt 0x80000000 DSPControl 0x100000
7 absq_s.ph $t2, $t4 :: rd 0x00010001 rt 0xffffffff DSPControl 0x0
8 absq_s.ph $t0, $t8 :: rd 0x000c5fff rt 0xfff45fff DSPControl 0x0
9 absq_s.ph $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0
10 absq_s.ph $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0
11 absq_s.ph $t2, $t3 :: rd 0x05555214 rt 0x0555adec DSPControl 0x
[all...] |
| mips32_dsp.stdout.exp-LE | 2 absq_s.ph $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0
3 absq_s.ph $t2, $t3 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0
4 absq_s.ph $t4, $t1 :: rd 0x05442435 rt 0xfabc2435 DSPControl 0x0
5 absq_s.ph $t6, $t7 :: rd 0x73467fff rt 0x73468000 DSPControl 0x100000
6 absq_s.ph $t5, $t3 :: rd 0x7fff0000 rt 0x80000000 DSPControl 0x100000
7 absq_s.ph $t2, $t4 :: rd 0x00010001 rt 0xffffffff DSPControl 0x0
8 absq_s.ph $t0, $t8 :: rd 0x000c5fff rt 0xfff45fff DSPControl 0x0
9 absq_s.ph $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0
10 absq_s.ph $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0
11 absq_s.ph $t2, $t3 :: rd 0x05555214 rt 0x0555adec DSPControl 0x
[all...] |
| mips32_dspr2.stdout.exp | 2 absq_s.qb $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0
3 absq_s.qb $t2, $t3 :: rd 0x0000027a rt 0x00000286 DSPControl 0x0
4 absq_s.qb $t4, $t1 :: rd 0x06442435 rt 0xfabc2435 DSPControl 0x0
5 absq_s.qb $t6, $t7 :: rd 0x73467f44 rt 0x734680bc DSPControl 0x100000
6 absq_s.qb $t5, $t3 :: rd 0x7f000000 rt 0x80000000 DSPControl 0x100000
7 absq_s.qb $t2, $t4 :: rd 0x01010101 rt 0xffffffff DSPControl 0x0
8 absq_s.qb $t0, $t8 :: rd 0x010c5f01 rt 0xfff45fff DSPControl 0x0
9 absq_s.qb $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0
10 absq_s.qb $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0
11 absq_s.qb $t2, $t3 :: rd 0x05555314 rt 0x0555adec DSPControl 0x
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_mips_toIR.c | 1031 /* Get value from DSPControl register (helper function for MIPS32 DSP ASE
1039 /* Put value to DSPControl register. Expression e is written to DSPControl as
1040 is. If only certain bits of DSPControl need to be changed, it should be done
1041 before calling putDSPControl(). It could be done by reading DSPControl and
[all...] |
| guest_mips_helpers.c | 169 vex_state->guest_DSPControl = 0; /* DSPControl register */
[all...] |
