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  /external/drm_gralloc/
gralloc_drm_radeon.c 64 int group_bytes; member in struct:radeon_info
88 pitch_align = (((info->group_bytes / 8) / bpe) *
94 pitch_align = MAX(8, (info->group_bytes / (8 * bpe)));
96 pitch_align = MAX(info->group_bytes / bpe, pitch_align);
100 pitch_align = MAX(64, info->group_bytes / bpe);
158 base_align = info->group_bytes;
383 info->group_bytes = 256;
386 info->group_bytes = 512;
426 info->group_bytes = 256;
429 info->group_bytes = 512
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  /external/libdrm/radeon/
radeon_surface.c 97 uint32_t group_bytes; member in struct:radeon_hw_info
248 surf_man->hw_info.group_bytes = 256;
251 surf_man->hw_info.group_bytes = 512;
254 surf_man->hw_info.group_bytes = 256;
270 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
304 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
340 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
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  /external/mesa3d/src/gallium/drivers/radeonsi/
r600.h 57 unsigned group_bytes; member in struct:r600_tiling_info
radeonsi_pipe.c 624 rscreen->tiling_info.group_bytes = 256;
627 rscreen->tiling_info.group_bytes = 512;
640 rscreen->tiling_info.group_bytes = 512;
  /external/mesa3d/src/gallium/drivers/r600/
r600_pipe.c 807 rscreen->tiling_info.group_bytes = 256;
810 rscreen->tiling_info.group_bytes = 512;
853 rscreen->tiling_info.group_bytes = 256;
856 rscreen->tiling_info.group_bytes = 512;
870 rscreen->tiling_info.group_bytes = 256;
872 rscreen->tiling_info.group_bytes = 512;
r600.h 78 unsigned group_bytes; member in struct:r600_tiling_info
r600_texture.c 336 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
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  /external/mesa3d/docs/
relnotes-7.10.html 151 <li>r600c/evergreen: texture align is group_bytes just like 6xx/7xx</li>
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