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  /external/llvm/lib/Target/AMDGPU/
AMDKernelCodeT.h 184 /// @brief The hsa_ext_control_directives_t specifies the values for the HSAIL
189 /// either came from the finalizer argument or explicit HSAIL control
192 /// arguments have to agree with the control directives in the HSAIL code.
202 /// non-0 and specifies the set of HSAIL exceptions that must have the BREAK
213 /// non-0 and specifies the set of HSAIL exceptions that must have the DETECT
233 /// calls, and group memory used to implement other HSAIL features such as
293 /// HSAIL operations.
493 /// access HSAIL Global/Readonly/Kernarg (which are combine) segments using a
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  /external/llvm/lib/Support/
Triple.cpp 58 case hsail: return "hsail";
123 case hsail:
124 case hsail64: return "hsail";
266 .Case("hsail", hsail)
374 .Case("hsail", Triple::hsail)
562 case Triple::hsail:
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  /external/llvm/unittests/ADT/
TripleTest.cpp 160 T = Triple("hsail-unknown-unknown");
161 EXPECT_EQ(Triple::hsail, T.getArch());
440 T.setArch(Triple::hsail);
556 T.setArch(Triple::hsail);
557 EXPECT_EQ(Triple::hsail, T.get32BitArchVariant().getArch());
561 EXPECT_EQ(Triple::hsail, T.get32BitArchVariant().getArch());
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  /external/llvm/include/llvm/ADT/
Triple.h 83 hsail, // AMD HSAIL enumerator in enum:llvm::Triple::ArchType
84 hsail64, // AMD HSAIL with 64-bit pointers

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