/art/compiler/utils/mips/ |
assembler_mips.cc | 780 void MipsAssembler::EmitBcondR6(BranchCondition cond, Register rs, Register rt, uint32_t imm16_21) { 783 Bltc(rs, rt, imm16_21); 786 Bgec(rs, rt, imm16_21); 789 Bgec(rt, rs, imm16_21); 792 Bltc(rt, rs, imm16_21); 796 Bltzc(rs, imm16_21); 800 Bgezc(rs, imm16_21); 804 Blezc(rs, imm16_21); 808 Bgtzc(rs, imm16_21); 811 Beqc(rs, rt, imm16_21); 832 Bc1eqz(static_cast<FRegister>(rs), imm16_21); local 836 Bc1nez(static_cast<FRegister>(rs), imm16_21); local [all...] |
assembler_mips.h | 770 void EmitBcondR6(BranchCondition cond, Register rs, Register rt, uint32_t imm16_21); [all...] |
/art/compiler/utils/mips64/ |
assembler_mips64.cc | 637 uint32_t imm16_21) { 640 Bltc(rs, rt, imm16_21); 643 Bgec(rs, rt, imm16_21); 646 Bgec(rt, rs, imm16_21); 649 Bltc(rt, rs, imm16_21); 653 Bltzc(rs, imm16_21); 657 Bgezc(rs, imm16_21); 661 Blezc(rs, imm16_21); 665 Bgtzc(rs, imm16_21); 668 Beqc(rs, rt, imm16_21); 689 Bc1eqz(static_cast<FpuRegister>(rs), imm16_21); local 693 Bc1nez(static_cast<FpuRegister>(rs), imm16_21); local [all...] |
assembler_mips64.h | 683 void EmitBcondc(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21);
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