/art/runtime/interpreter/mterp/x86/ |
op_add_long.S | 1 %include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4), rIBASE", "instr2":"adcl 4(rFP,%ecx,4), %eax"}
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op_add_long_2addr.S | 1 %include "x86/binopWide2addr.S" {"instr1":"addl %eax, (rFP,rINST,4)","instr2":"adcl %ecx, 4(rFP,rINST,4)"}
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op_and_long.S | 1 %include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4), rIBASE", "instr2":"andl 4(rFP,%ecx,4), %eax"}
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op_and_long_2addr.S | 1 %include "x86/binopWide2addr.S" {"instr1":"andl %eax, (rFP,rINST,4)","instr2":"andl %ecx, 4(rFP,rINST,4)"}
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op_or_long.S | 1 %include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4), rIBASE", "instr2":"orl 4(rFP,%ecx,4), %eax"}
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op_or_long_2addr.S | 1 %include "x86/binopWide2addr.S" {"instr1":"orl %eax, (rFP,rINST,4)","instr2":"orl %ecx, 4(rFP,rINST,4)"}
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op_sub_long.S | 1 %include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4), rIBASE", "instr2":"sbbl 4(rFP,%ecx,4), %eax"}
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op_sub_long_2addr.S | 1 %include "x86/binopWide2addr.S" {"instr1":"subl %eax, (rFP,rINST,4)","instr2":"sbbl %ecx, 4(rFP,rINST,4)"}
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op_xor_long.S | 1 %include "x86/binopWide.S" {"instr1":"xorl (rFP,%ecx,4), rIBASE", "instr2":"xorl 4(rFP,%ecx,4), %eax"}
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op_xor_long_2addr.S | 1 %include "x86/binopWide2addr.S" {"instr1":"xorl %eax, (rFP,rINST,4)","instr2":"xorl %ecx, 4(rFP,rINST,4)"}
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binopWide.S | 11 $instr2 # ex: adcl 4(rFP,%ecx,4),%eax
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binopWide2addr.S | 11 $instr2 # ex: adcl %ecx,4(rFP,rINST,4)
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/external/compiler-rt/test/profile/ |
instrprof-shared.test | 6 3. libt-no-instr2.so is compiled with instrumentation enabled, but the object file is built 19 RUN: %clang -c -o %t.d/instrprof-shared-lib-no-instr2.o -fPIC %S/Inputs/instrprof-shared-lib.c 20 RUN: %clang_profgen -o %t.d/libt-no-instr2.so -fPIC -shared %t.d/instrprof-shared-lib-no-instr2.o 24 RUN: %clang_profgen -o %t-instr-no-instr2 -L%t.d -rpath %t.d -lt-no-instr2 %S/Inputs/instrprof-shared-main.c 27 RUN: %clang -o %t-no-instr1-no-instr2 -L%t.d -rpath %t.d -lt-no-instr2 %S/Inputs/instrprof-shared-main.c 28 RUN: %clang -c -o %t.d/instrprof-shared-main-no-instr2.o %S/Inputs/instrprof-shared-main.c 29 RUN: %clang -o %t-no-instr2-instr -L%t.d -rpath %t.d -lt-instr %t.d/instrprof-shared-main-no-instr2. [all...] |
/external/v8/src/arm64/ |
code-stubs-arm64.h | 106 Instruction* instr2 = instr1->following(); local 109 DCHECK(instr2->IsPCRelAddressing() && (instr2->Rd() == xzr.code())); 115 if (instr2->IsUncondBranchImm()) { 119 DCHECK(instr2->IsPCRelAddressing()); 137 Instruction* instr2 = patcher.InstructionAt(kInstructionSize); local 140 DCHECK(instr2->IsPCRelAddressing() || instr2->IsUncondBranchImm()); 145 static_cast<int32_t>(instr2->ImmPCOffset());
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/external/v8/src/ppc/ |
assembler-ppc-inl.h | 493 Instr instr2 = instr_at(pc + kInstrSize); local 495 if (IsLis(instr1) && IsOri(instr2)) { 501 static_cast<uint32_t>(instr2 & kImm16Mask)); 508 (instr2 & kImm16Mask)); 612 Instr instr2 = instr_at(pc + kInstrSize); local 615 instr2 &= ~kImm16Mask; 616 instr2 |= (lo_word & kImm16Mask); 618 instr_at_put(pc + kInstrSize, instr2); 673 Instr instr2 = instr_at(pc + kInstrSize); local 675 if (IsLis(instr1) && IsOri(instr2)) { [all...] |
assembler-ppc.cc | 293 bool Assembler::Is64BitLoadIntoR12(Instr instr1, Instr instr2, Instr instr3, 301 return (((instr1 >> 16) == 0x3d80) && ((instr2 >> 16) == 0x618c) && 307 bool Assembler::Is32BitLoadIntoR12(Instr instr1, Instr instr2) { 311 return (((instr1 >> 16) == 0x3d80) && ((instr2 >> 16) == 0x618c)); [all...] |
/external/v8/src/compiler/ |
instruction-scheduler.cc | 231 const Instruction* instr1, const Instruction* instr2) const { 233 for (size_t j = 0; j < instr2->InputCount(); ++j) { 235 const InstructionOperand* input = instr2->InputAt(j);
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instruction-scheduler.h | 104 // Return true if instr2 uses any value defined by instr1. 106 const Instruction* instr2) const;
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/external/icu/icu4c/source/test/iotest/ |
stream.cpp | 59 UnicodeString inStr2; 104 inTestStream >> inStr >> inStr2; 110 if (inStr2.compare(mu) != 0) {
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/external/v8/src/mips/ |
assembler-mips-inl.h | 357 Instr instr2 = Assembler::instr_at(pc_ + 2 * Assembler::kInstrSize); local 360 ((instr2 & kOpcodeMask) == JAL || 361 ((instr2 & kOpcodeMask) == SPECIAL && 362 (instr2 & kFunctionFieldMask) == JALR)));
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assembler-mips.cc | 3001 Instr instr2 = instr_at(pc + kInstrSize); local 3034 Instr instr2 = instr_at(pc + kInstrSize); local [all...] |
/external/v8/src/mips64/ |
assembler-mips64-inl.h | 355 Instr instr2 = Assembler::instr_at(pc_ + 2 * Assembler::kInstrSize); // dsll. local 361 (instr2 & kFunctionFieldMask) == DSLL &&
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/external/llvm/docs/ |
MergeFunctions.rst | 415 instr0 i32 %pf0 instr1 i32 %pf1 instr2 i32 123 421 instr0 i32 %pg0 instr1 i32 %pg0 instr2 i32 123 434 And instructions with opcode "*instr2*" are equal, because their opcodes and
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/external/llvm/utils/TableGen/ |
CodeGenMapTable.cpp | 47 // Ex: RowInstrMap(RowVal1, RowVal2, ...) -> [Instr1, Instr2, Instr3, ... ] 48 // Here Instr1, Instr2, Instr3 have same values (RowVal1, RowVal2) for
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/external/llvm/lib/Target/Hexagon/ |
HexagonExpandCondsets.cpp | [all...] |