/art/runtime/interpreter/mterp/x86/ |
op_mul_double.S | 1 %include "x86/sseBinop.S" {"instr":"muls","suff":"d"}
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op_mul_double_2addr.S | 1 %include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"d"}
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op_mul_float.S | 1 %include "x86/sseBinop.S" {"instr":"muls","suff":"s"}
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op_mul_float_2addr.S | 1 %include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"s"}
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/art/runtime/interpreter/mterp/x86_64/ |
op_mul_double.S | 1 %include "x86_64/sseBinop.S" {"instr":"muls","suff":"d"}
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op_mul_double_2addr.S | 1 %include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"d"}
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op_mul_float.S | 1 %include "x86_64/sseBinop.S" {"instr":"muls","suff":"s"}
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op_mul_float_2addr.S | 1 %include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"s"}
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
thumb2_mul-bad.s | 14 # There is no conditional "muls". 16 # There is no 32-bit "muls". 17 muls.w r0, r0, r1 18 # Cannot use high registers with "muls". 19 muls r0, r0, r8 20 muls r0, r8, r0
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thumb2_mul-bad.l | 6 [^:]*:17: Error: Thumb-2 MUL must not set flags -- `muls.w r0,r0,r1' 7 [^:]*:19: Error: Thumb-2 MUL must not set flags -- `muls r0,r0,r8' 8 [^:]*:20: Error: Thumb-2 MUL must not set flags -- `muls r0,r8,r0'
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tcompat2.d | 17 0+0c <[^>]*> 4348 * muls r0, r1 18 0+0e <[^>]*> 4348 * muls r0, r1
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arm-it-auto.s | 106 muls r0, r0, r1 label 110 muls r0, r0, r1 label
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
mulbug-err-1.s | 9 muls.w $r1,$r4 ; { dg-error "align" } 11 muls.b $r1,$r4 ; { dg-error "align" } 17 muls.w $r1,$r4 ; { dg-error "align" } 20 muls.d $r1,$r4 ; { dg-error "align" } 28 muls.d $r1,$r4 34 muls.w $r1,$r4 49 muls.d $r1,$r4 54 muls.w $r1,$r4 56 muls.b $r4,$r1
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/external/llvm/test/CodeGen/Thumb2/ |
thumb2-mla.ll | 13 ; NO_MULOPS: muls r0, r1, r0 24 ; NO_MULOPS: muls r0, r1, r0
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thumb2-mls.ll | 18 ; CHECK: muls r0, r1, r0
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thumb2-mul.ll | 5 ; CHECK: muls r0, r1, r0
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/external/llvm/test/CodeGen/ARM/ |
shifter_operand.ll | 71 ; CHECK-THUMB: muls r1, r2, r1 82 ; CHECK-THUMB: muls r1, r2, r1 94 ; CHECK-THUMB: muls r1, r2, r1 106 ; CHECK-THUMB: muls r1, r2, r1 118 ; CHECK-THUMB: muls r1, r2, r1 130 ; CHECK-THUMB: muls r1, r2, r1 142 ; CHECK-THUMB: muls r1, r2, r1 156 ; CHECK-THUMB: muls r1, r2, r1 170 ; CHECK-THUMB: muls r1, r2, r1 184 ; CHECK-THUMB: muls r1, r2, r [all...] |
avoid-cpsr-rmw.ll | 10 ; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2 12 ; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0 14 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]] 31 ; CHECK-NOT: muls 64 ; CHECK: muls
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gep-optimization.ll | 12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]] 36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]] 60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
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/external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/ |
fft.c | 160 //This mul segment needs 6*8 = 48 cycles for 16x16 muls, but 6*20 = 120 cycles for 16x32 muls 164 /* Complexity is: 51+48 = 99 cycles for 16x16 muls, but 51+120 = 171 cycles for 16x32 muls*/ 197 /* Complexity : (31+6)*20 = 740 cycles for 16x16 muls, but (31+18)*20 = 980 cycles for 16x32 muls*/ 202 /* Complexity : 4*(740+3) = 2972 cycles for 16x16 muls, but 4*(980+3) = 3932 cycles for 16x32 muls*/ 234 // Complexity: 2*(13+5+4*13+2) = 144 for 16x16 muls, but 2*(13+5+4*33+2) = 304 cycles for 16x32 muls [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/h8300/ |
t06_ari2.s | 159 muls.w #0xf:4,r1 ;01c650f1
161 muls.w r3,r1 ;01c25031
163 muls.l #0xf:4,er1 ;01c652f1
165 muls.l er3,er1 ;01c25231
167 muls/u.l #0xf:4,er1 ;01c752f1
169 muls/u.l er3,er1 ;01c35231
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/external/llvm/test/MC/ARM/ |
mul-v4.s | 6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0] 10 muls r0, r1, r2 label
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
mips64-mdmx.s | 125 muls.ob $v12, 18 126 muls.ob $v12, $v18 127 muls.ob $v12, $v18[6] 129 muls.qh $v12, 18 130 muls.qh $v12, $v18 131 muls.qh $v12, $v18[2]
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vr5400.s | 11 muls $4,$5,$6 86 nsel2 muls.ob
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sb1-ext-mdmx.s | 74 muls.ob $v12, 18 75 muls.ob $v12, $v18 76 muls.ob $v12, $v18[6]
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