| /art/runtime/interpreter/mterp/mips/ |
| op_mul_long_2addr.S | 19 multu a2, a0
|
| op_mul_long.S | 27 multu a2, a0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/dlx/ |
| rtype.s | 8 multu t4,t2,t3
|
| rtype.d | 16 18: 01 4b 60 06 multu r12,r10,r11
24 38: 01 bf 78 06 multu r15,r13,r31
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| elf_e_flags1.d | 14 0: 00850019 multu a0,a1
|
| mul-ilocks.d | 11 0+0000 <[^>]*> multu a0,a1
13 0+0008 <[^>]*> multu a1,a2
50 0+009c <[^>]*> multu a0,a1
56 0+00b4 <[^>]*> multu a1,a2
|
| mul.d | 10 0+0000 <[^>]*> multu a0,a1
13 0+0010 <[^>]*> multu a1,a2
58 0+00d0 <[^>]*> multu a0,a1
64 0+00e8 <[^>]*> multu a1,a2
|
| vr4120-2.s | 73 multu $4,$5
89 multu $4,$5
|
| r5900.d | 74 [0-9a-f]+ <[^>]*> 001f0019 multu \$0,\$31
75 [0-9a-f]+ <[^>]*> 03e0f819 multu \$31,\$31,\$0
76 [0-9a-f]+ <[^>]*> 001f0019 multu \$0,\$31
77 [0-9a-f]+ <[^>]*> 03e0f819 multu \$31,\$31,\$0
|
| r5900.s | 106 multu $0, $0, $31
107 multu $31, $31, $0
|
| vr4120-2.d | 78 .* <[^>]*> multu a0,a1
98 .* <[^>]*> multu a0,a1
|
| mips32-dspr2.s | 36 multu $ac0,$22,$23
|
| /external/llvm/test/CodeGen/Mips/ |
| mulll.ll | 13 ; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
|
| mulull.ll | 14 ; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
|
| 2008-08-01-AsmInline.ll | 8 ; CHECK: multu
11 %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 23 multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips2.s | 29 multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1.s | 26 multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips3.s | 22 multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips2.s | 32 multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 43 multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/mips32/ |
| MIPS32int.stdout.exp-mips32-BE | 491 MULTU
492 multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
493 multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
494 multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
495 multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
496 multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
497 multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
498 multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
499 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
500 multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
[all...] |
| MIPS32int.stdout.exp-mips32-LE | 491 MULTU
492 multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
493 multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
494 multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
495 multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
496 multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
497 multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
498 multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
499 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
500 multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-alu-instructions.s | 38 # CHECK-EL: multu $9, $7 # encoding: [0xe9,0x00,0x3c,0x9b]
75 # CHECK-EB: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c]
110 multu $9, $7
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 12 MUL, MULT, MULTU, MOVN,
251 case MULTU:
255 TEST4("multu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
|
