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  /art/runtime/interpreter/mterp/arm/
op_goto_32.S 15 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa
binopWide.S 28 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
binopWide2addr.S 24 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
tcompat2.d 19 0+10 <[^>]*> 4308 * orrs r0, r1
20 0+12 <[^>]*> 4308 * orrs r0, r1
armv1.s 21 orrs r0, r0, r0
thumb2_it.s 23 orrs r0, r0, r2
thumb2_it.d 26 0+02c <[^>]+> 4310 orrs r0, r2
thumb2_it_auto.d 26 0+02c <[^>]+> 4310 orrs r0, r2
armv1.d 28 0+44 <[^>]*> e1900000 ? orrs r0, r0, r0
  /external/llvm/test/MC/ARM/
thumb_rewrites.s 92 orrs r0, r0, r1
93 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
95 orrs r0, r1, r0
96 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
thumb2-narrow-dp.ll     [all...]
  /ndk/tests/device/bitfield/jni/
func.c 19 * 26: 4308 orrs r0, r1
  /external/llvm/test/CodeGen/ARM/
2011-04-15-RegisterCmpPeephole.ll 23 ; CHECK: orrs
fast-isel-binary.ll 52 ; THUMB: orrs r0, r1
64 ; THUMB: orrs r0, r1
76 ; THUMB: orrs r0, r1
movcc-double.ll 41 ; CHECK: orrs
select_xform.ll 298 ; T2: orrs r0, {{r[0-9]+}}
313 ; T2: orrs r0, {{r[0-9]+}}
  /device/google/contexthub/firmware/src/cpu/cortexm4f/
atomicBitset.c 75 " orrs %0, %3 \n"
99 " orrs %0, %3 \n"
  /external/llvm/test/CodeGen/Thumb2/
thumb2-orr.ll 5 ; CHECK: orrs r0, r1
thumb2-uxtb.ll 127 ; ARMv7A: orrs r0, r1
134 ; ARMv7M: orrs r0, r1
  /external/valgrind/none/tests/arm/
v6intThumb.c     [all...]
v6intThumb.stdout.exp 140 ORRS-16 0x10C
141 orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 0, cpsr 0x00000000
142 orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
143 orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
144 orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
145 orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
146 orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
147 orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
148 orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
149 orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z
    [all...]
  /external/compiler-rt/lib/builtins/arm/
comparesf2.S 55 orrs r12, r2, r3, lsr #1
76 // still clear from the shift argument in orrs; if a is positive and b
116 orrs r12, r2, r3, lsr #1
  /system/core/libpixelflinger/
t32cb16blend.S 169 orrs r3, r4, r5
188 orrs r3, r4, r5
  /bionic/libc/arch-arm/generic/bionic/
memcmp.S 87 orrs r3, ip
98 orrs r3, ip
  /art/compiler/utils/arm/
assembler_arm32_test.cc 743 TEST_F(AssemblerArm32Test, Orrs) {
744 T4Helper(&arm::Arm32Assembler::orrs, true, "orr{cond}s {reg1}, {reg2}, {shift}", "orrs");

Completed in 795 milliseconds

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