| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fp-imm.ll | 8 ; CHECK: ldr d0, [x[[REG]], lCPI0_0@PAGEOFF]
18 ; CHECK: ldr s0, [x[[REG]], lCPI1_0@PAGEOFF]
29 ; CHECK: ldr q0, [x[[REG]], lCPI2_0@PAGEOFF]
|
| global-merge-ignore-single-use-minsize.ll | 15 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
30 ; CHECK-NEXT: str w0, [x8, _m2@PAGEOFF]
31 ; CHECK-NEXT: str w1, [x9, _n2@PAGEOFF]
48 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
61 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
64 ; CHECK-NEXT: str w1, [x9, _n4@PAGEOFF]
|
| global-merge-ignore-single-use.ll | 14 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
28 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
41 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
54 ; CHECK-NEXT: str w0, [x8, _o2@PAGEOFF]
|
| arm64-fast-isel-materialize.ll | 32 ; CHECK-NEXT: ldr s0, {{\[}}[[REG]], {{lCPI[0-9]+_0}}@PAGEOFF{{\]}}
39 ; CHECK-NEXT: ldr d0, {{\[}}[[REG]], {{lCPI[0-9]+_0}}@PAGEOFF{{\]}}
|
| arm64-fast-isel-intrinsic.ll | 9 ; ARM64: add x0, x8, _message@PAGEOFF
25 ; ARM64: add x1, x8, _message@PAGEOFF
39 ; ARM64: add x1, x8, _message@PAGEOFF
53 ; ARM64: add x9, x9, _message@PAGEOFF
70 ; ARM64: add x9, x9, _message@PAGEOFF
87 ; ARM64: add x9, x9, _message@PAGEOFF
104 ; ARM64: add x9, x9, _message@PAGEOFF
123 ; ARM64: add x9, x9, _message@PAGEOFF
|
| global-merge-group-by-use.ll | 16 ; CHECK-NEXT: add x8, x8, [[SET1]]@PAGEOFF
31 ; CHECK-NEXT: add x8, x8, [[SET2]]@PAGEOFF
52 ; CHECK-NEXT: str w0, [x8, _m3@PAGEOFF]
53 ; CHECK-NEXT: str w1, [x9, [[SET3]]@PAGEOFF]
66 ; CHECK-NEXT: add x8, x8, [[SET3]]@PAGEOFF
82 ; CHECK-NEXT: str w0, [x8, _o5@PAGEOFF]
|
| global-merge-2.ll | 13 ;CHECK-APPLE-IOS: add x8, x8, l__MergedGlobals@PAGEOFF
23 ;CHECK-APPLE-IOS: add x8, x8, l__MergedGlobals@PAGEOFF
|
| arm64-2012-05-07-MemcpyAlignBug.ll | 10 ; CHECK: add x[[ADDR:[0-9]+]], x[[PAGE]], {{l_b@PAGEOFF|:lo12:.Lb}}
|
| arm64-jumptable.ll | 31 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0@PAGEOFF
|
| arm64-vshuffle.ll | 28 ; CHECK: ldr d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
67 ; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
|
| global-merge-3.ll | 12 ;CHECK-APPLE-IOS: add x8, x8, l__MergedGlobals@PAGEOFF
14 ;CHECK-APPLE-IOS: add x9, x9, l__MergedGlobals.1@PAGEOFF
|
| arm64-blockaddress.ll | 11 ; CHECK: add {{x[0-9]+}}, [[REG]], Ltmp1@PAGEOFF
|
| arm64-hello.ll | 10 ; CHECK: add x0, x0, L_.str@PAGEOFF
|
| arm64-swizzle-tbl-i16-layout.ll | 30 ; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF]
|
| arm64-promote-const.ll | 15 ; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF
26 ; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
28 ; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
30 ; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF]
32 ; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF]
44 ; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
55 ; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
|
| arm64-setcc-int-to-fp-combine.ll | 39 ; CHECK: ldr q2, [x8, lCPI2_0@PAGEOFF]
|
| /external/llvm/test/CodeGen/MIR/AArch64/ |
| target-flags.mir | 26 ; CHECK-NEXT: %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
27 ; CHECK-NEXT: %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
29 ; CHECK: STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
32 %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
33 %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
37 STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
|
| expected-target-flag-name.mir | 21 %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ) @var_i32
|
| invalid-target-flag-name.mir | 21 %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ncc) @var_i32
|
| /external/llvm/test/MC/MachO/AArch64/ |
| reloc-crash2.s | 18 ldr x0, [x8, L_bar@PAGEOFF]
|
| darwin-ARM64-reloc.s | 9 ldr w2, [x3, _data@pageoff]
11 add x3, x3, _data@pageoff + 4
14 ldr w2, [x3, _data@pageoff + 4]
|
| /external/llvm/test/tools/llvm-objdump/AArch64/ |
| macho-symbolized-disassembly.test | 7 OBJ: 0000000000000020 add x0, x0, L_.str@PAGEOFF
15 ObjC-OBJ: 0000000000000010 add x8, x8, L_OBJC_SELECTOR_REFERENCES_3@PAGEOFF
|
| /external/llvm/include/llvm/MC/ |
| MCLinkerOptimizationHint.h | 35 MCLOH_AdrpLdr = 0x2u, ///< Adrp _v@PAGE -> Ldr _v@PAGEOFF.
36 MCLOH_AdrpAddLdr = 0x3u, ///< Adrp _v@PAGE -> Add _v@PAGEOFF -> Ldr.
38 MCLOH_AdrpAddStr = 0x5u, ///< Adrp _v@PAGE -> Add _v@PAGEOFF -> Str.
40 MCLOH_AdrpAdd = 0x7u, ///< Adrp _v@PAGE -> Add _v@PAGEOFF.
|
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 276 add w3, w5, sym@PAGEOFF
278 ; CHECK-ERRORS: add w3, w5, sym@PAGEOFF
281 adds w3, w5, sym@PAGEOFF
282 adds x9, x12, sym@PAGEOFF
284 ; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF
287 ; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF
290 sub x3, x5, sym@PAGEOFF
291 sub w20, w30, sym@PAGEOFF
293 ; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF
296 ; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF
[all...] |
| /external/llvm/test/ExecutionEngine/RuntimeDyld/AArch64/ |
| MachO_ARM64_relocations.s | 38 ldr x0, [x0, _ptr@PAGEOFF]
63 add x0, x0, tgt@PAGEOFF+8
|
