| /external/libhevc/common/arm64/ |
| ihevc_weighted_pred_bi_default.s | 205 sqshrun v20.8b, v18.8h,#7
217 sqshrun v30.8b, v30.8h,#7
260 sqshrun v20.8b, v18.8h,#7
303 sqshrun v20.8b, v24.8h,#7
306 sqshrun v21.8b, v22.8h,#7
313 sqshrun v30.8b, v30.8h,#7
314 sqshrun v31.8b, v1.8h,#7
362 sqshrun v20.8b, v24.8h,#7
363 sqshrun v21.8b, v22.8h,#7
446 sqshrun v20.8b, v22.8h,#
[all...] |
| ihevc_intra_pred_luma_dc.s | 243 sqshrun v2.8b, v20.8h,#2 //columns shx2 movn (prol)
249 sqshrun v3.8b, v22.8h,#2 //rows shx2 movn (prol)
269 sqshrun v4.8b, v26.8h,#2 //columns shx2 movn (prol extra)
327 sqshrun v3.8b, v22.8h,#2 //rows shx2 movn (prol)
479 sqshrun v2.8b, v20.8h,#2 //columns shx2 movn (prol)
482 sqshrun v3.8b, v22.8h,#2 //rows shx2 movn (prol)
|
| /external/llvm/test/MC/AArch64/ |
| neon-scalar-shift-imm.s | 168 sqshrun b15, h10, #7
169 sqshrun h20, s14, #3
170 sqshrun s10, d15, #15
172 // CHECK: sqshrun b15, h10, #7 // encoding: [0x4f,0x85,0x09,0x7f]
173 // CHECK: sqshrun h20, s14, #3 // encoding: [0xd4,0x85,0x1d,0x7f]
174 // CHECK: sqshrun s10, d15, #15 // encoding: [0xea,0x85,0x31,0x7f]
|
| arm64-advsimd.s | [all...] |
| neon-simd-shift.s | 279 sqshrun v0.8b, v1.8h, #3
280 sqshrun v0.4h, v1.4s, #3
281 sqshrun v0.2s, v1.2d, #3
286 // CHECK: sqshrun v0.8b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x2f]
287 // CHECK: sqshrun v0.4h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x2f]
288 // CHECK: sqshrun v0.2s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x2f]
|
| neon-diagnostics.s | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_ColorMatrix.S | 88 sqshrun v8.4h, v6.4s, #8
105 sqshrun v8.4h, v6.4s, #8
123 sqshrun v9.4h, v6.4s, #8
140 sqshrun v9.4h, v6.4s, #8
158 sqshrun v10.4h, v6.4s, #8
175 sqshrun v10.4h, v6.4s, #8
193 sqshrun v11.4h, v6.4s, #8
210 sqshrun v11.4h, v6.4s, #8
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-simd-shift.ll | 336 %vqshrun = tail call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %b, i32 3)
347 %vqshrun = tail call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %b, i32 9)
359 %vqshrun = tail call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %b, i32 19)
566 declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, i32)
568 declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, i32)
570 declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, i32)
|
| arm64-vshift.ll | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| neon-instructions.txt | [all...] |
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| row_neon64.cc | 111 "sqshrun v0.4h, v0.4s, #16 \n" \
128 "sqshrun " #vB ".8b, " #vB ".8h, #6 \n" /* B */ \
129 "sqshrun " #vG ".8b, " #vG ".8h, #6 \n" /* G */ \
130 "sqshrun " #vR ".8b, " #vR ".8h, #6 \n" /* R */ \
[all...] |
| /frameworks/rs/driver/runtime/arch/ |
| asimd.ll | 30 declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
31 declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
32 declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
[all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| aarch64-tbl.h | 343 /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
[all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.c | 781 case ARM64vecshi_SQSHRUN2SD: *nm = "sqshrun"; *ar = "2sd"; return;
782 case ARM64vecshi_SQSHRUN4HS: *nm = "sqshrun"; *ar = "4hs"; return;
783 case ARM64vecshi_SQSHRUN8BH: *nm = "sqshrun"; *ar = "8bh"; return;
[all...] |
