| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_64.c | 35 sljit_uw uimm; local
49 uimm = imm;
51 uimm = ~imm;
55 while (!(uimm & 0xff00000000000000l)) {
57 uimm <<= 8;
60 if (!(uimm & 0xf000000000000000l)) {
62 uimm <<= 4;
65 if (!(uimm & 0xc000000000000000l)) {
67 uimm <<= 2;
70 if ((sljit_sw)uimm < 0)
[all...] |
| sljitNativeARM_64.c | 352 sljit_uw mask, uimm; local
365 uimm = (sljit_uw)imm;
372 if ((uimm & mask) != ((uimm >> len) & mask))
380 if (uimm & 0x1) {
382 uimm = ~uimm;
386 uimm &= ((sljit_uw)1 << len) - 1;
389 COUNT_TRAILING_ZERO(uimm, right);
392 imm = (sljit_sw)~uimm;
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| lm32.cpu | 128 (dnf f-uimm "unsigned immediate field" () 15 16)
151 (dnop uimm "unsigned immediate" () h-uint f-uimm)
163 (index f-uimm)
172 (index f-uimm)
308 "andi $r1,$r0,$uimm"
309 (+ OP_ANDI r0 r1 uimm)
310 (set r1 (and r0 (zext SI uimm)))
459 "cmpgeui $r1,$r0,$uimm"
460 (+ OP_CMPGEUI r0 r1 uimm)
[all...] |
| or1korbis.cpu | 896 (define-pmacro (alu-insn-uimm mnemonic)
909 (alu-insn-uimm and)
910 (alu-insn-uimm or)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 99 static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI,
116 const unsigned Imm16 = getChunk(UImm, ChunkIdx);
150 static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
159 ++Counts[getChunk(UImm, Idx)];
189 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
214 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
284 static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
295 int64_t Chunk = getChunk(UImm, Idx);
322 uint64_t OrrImm = UImm;
329 const uint64_t Chunk = getChunk(UImm, Idx)
[all...] |
| AArch64InstrInfo.cpp | 538 uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
540 return AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding);
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| lm32-opc.c | 169 /* andi $r1,$r0,$uimm */
172 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } },
283 /* cmpgeui $r1,$r0,$uimm */
286 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } },
295 /* cmpgui $r1,$r0,$uimm */
298 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } },
373 /* nori $r1,$r0,$uimm */
376 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } },
493 /* xori $r1,$r0,$uimm */
496 { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }
[all...] |
| lm32-desc.c | 248 { LM32_F_UIMM, "f-uimm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
299 /* uimm: unsigned immediate */
300 { "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
382 /* andi $r1,$r0,$uimm */
477 /* cmpgeui $r1,$r0,$uimm */
487 /* cmpgui $r1,$r0,$uimm */
552 /* nori $r1,$r0,$uimm */
652 /* xori $r1,$r0,$uimm */
662 /* xnori $r1,$r0,$uimm */
[all...] |
| lm32-opinst.c | 60 { INPUT, "uimm", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM), 0, 0 },
|
| ppc-opc.c | 577 /* The other UIMM field in a EVX form instruction. */
626 /* The 4-bit UIMM field in a VX form instruction. */
696 /* The UIMM field in a VX form instruction. */
697 #define UIMM SIMM + 1
698 #define DCTL UIMM
701 /* The 3-bit UIMM field in a VX form instruction. */
702 #define UIMM3 UIMM + 1
717 /* The other UIMM field in a half word EVX form instruction. */
721 /* The other UIMM field in a word EVX form instruction. */
725 /* The other UIMM field in a double EVX form instruction. *
[all...] |
| aarch64-opc.c | 1677 uint64_t uimm = opnd->imm.value; local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrAltivec.td | 518 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
519 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
521 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
522 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
523 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
525 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
526 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
527 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
529 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
530 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB)
[all...] |
| /external/llvm/lib/Target/SystemZ/InstPrinter/ |
| SystemZInstPrinter.cpp | 66 assert(isUInt<N>(Value) && "Invalid uimm argument");
|
| /external/valgrind/none/tests/ppc32/ |
| jm-insns.c | [all...] |
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/ppc64/ |
| asm9.go | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/ppc64/ |
| asm9.go | [all...] |
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/ppc64/ |
| asm9.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/internal/obj/ppc64/ |
| asm9.go | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.td | 403 let DiagnosticType = "UImm" # Bits # "_" # Offset;
530 def uimm # I : Operand<i32> {
579 def uimm # I # _64 : Operand<i64> {
[all...] |
| /prebuilts/go/darwin-x86/pkg/bootstrap/pkg/darwin_amd64/bootstrap/internal/obj/ |
| ppc64.a | 473 func @"".LOP_IRR (@"".op·2 uint32, @"".a·3 uint32, @"".s·4 uint32, @"".uimm·5 uint32) (? uint32) { return @"".op·2 | @"".s·4 & 0x1f << 0x15 | @"".a·3 & 0x1f << 0x10 | @"".uimm·5 & 0xffff }
[all...] |
| /prebuilts/go/darwin-x86/pkg/darwin_amd64/cmd/internal/obj/ |
| ppc64.a | 473 func @"".LOP_IRR (@"".op·2 uint32, @"".a·3 uint32, @"".s·4 uint32, @"".uimm·5 uint32) (? uint32) { return @"".op·2 | @"".s·4 & 0x1f << 0x15 | @"".a·3 & 0x1f << 0x10 | @"".uimm·5 & 0xffff }
[all...] |
| /prebuilts/go/linux-x86/pkg/bootstrap/pkg/linux_amd64/bootstrap/internal/obj/ |
| ppc64.a | 473 func @"".LOP_IRR (@"".op·2 uint32, @"".a·3 uint32, @"".s·4 uint32, @"".uimm·5 uint32) (? uint32) { return @"".op·2 | @"".s·4 & 0x1f << 0x15 | @"".a·3 & 0x1f << 0x10 | @"".uimm·5 & 0xffff }
[all...] |
| /prebuilts/go/linux-x86/pkg/linux_amd64/cmd/internal/obj/ |
| ppc64.a | 473 func @"".LOP_IRR (@"".op·2 uint32, @"".a·3 uint32, @"".s·4 uint32, @"".uimm·5 uint32) (? uint32) { return @"".op·2 | @"".s·4 & 0x1f << 0x15 | @"".a·3 & 0x1f << 0x10 | @"".uimm·5 & 0xffff }
[all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_isel.c | 891 ULong uimm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; local
893 if (0 == (uimm & (szB-1)) /* "uimm is szB-aligned" */
894 && (uimm >> szBbits) < 4096) {
896 return ARM64AMode_RI12(reg, (UInt)(uimm >> szBbits), (UChar)szB);
[all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| elf32-rx.c | [all...] |
