| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
| shar.sm | 1 shar #{uimm5},{reg}
3 shar #{uimm5},{reg},{reg}
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| shll.sm | 1 shll #{uimm5},{reg}
3 shll #{uimm5},{reg},{reg}
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| shlr.sm | 1 shlr #{uimm5},{reg}
3 shlr #{uimm5},{reg},{reg}
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| rotl.sm | 1 rotl #{uimm5},{reg}
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| rotr.sm | 1 rotr #{uimm5},{reg}
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| bmcnd.sm | 2 bm{cnd} #{uimm5}, {reg}
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| bclr.sm | 4 bclr #{uimm5}, {reg}
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| bnot.sm | 4 bnot #{uimm5}, {reg}
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| bset.sm | 4 bset #{uimm5}, {reg}
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| btst.sm | 4 btst #{uimm5}, {reg}
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| macros.inc | 20 macro uimm5 {0;31}
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| bit2.s | 9 //BITCLR ( Dreg , uimm5 ) ; /* (a) */
17 //BITSET ( Dreg , uimm5 ) ; /* (a) */
25 //BITTGL ( Dreg , uimm5 ) ; /* (a) */
33 //CC = BITTST ( Dreg , uimm5 ) ; /* set CC if bit = 1 (a)*/
41 //CC = ! BITTST ( Dreg , uimm5 ) ; /* set CC if bit = 0 (a)*/
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| shift2.s | 66 //Dreg >>>= uimm5 ; /* arithmetic right shift (a) */
74 //Dreg <<= uimm5 ; /* logical left shift (a) */
136 //Dreg = Dreg >>> uimm5 ; /* arithmetic right shift (b) */
150 //Dreg = Dreg << uimm5 (S) ; /* arithmetic left shift (b) */
163 //A0 = A0 >>> uimm5 ; /* arithmetic right shift (b) */
168 //A0 = A0 << uimm5 ; /* logical left shift (b) */
173 //A1 = A1 >>> uimm5 ; /* arithmetic right shift (b) */
178 //A1 = A1 << uimm5 ; /* logical left shift (b) */
|
| /external/llvm/test/MC/Mips/dsp/ |
| invalid.s | 10 // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
17 // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
|
| /external/llvm/test/MC/Mips/micromips-dsp/ |
| invalid.s | 10 // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
17 // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 151 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
153 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
155 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
164 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
279 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>,
281 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>,
289 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
322 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
657 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>
[all...] |
| MicroMips64r6InstrInfo.td | 71 class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5,
73 class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
|
| MipsSEISelDAGToDAG.h | 94 /// \brief Select constant vector splats whose value fits in a uimm5.
|
| MicroMipsInstrInfo.td | 506 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
720 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
722 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
724 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
732 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
[all...] |
| MipsISelDAGToDAG.h | 97 /// \brief Select constant vector splats whose value fits in a uimm5.
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| bfin-parse.y | 213 #define uimm5(x) EXPR_VALUE (x)
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| mep-core.cpu | 766 (dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8)
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| m32r-desc.c | 275 { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
357 /* uimm5: 5 bit shift count */
358 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
[all...] |
| m32r-opc.c | 882 /* slli $dr,$uimm5 */
885 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
900 /* srai $dr,$uimm5 */
903 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
918 /* srli $dr,$uimm5 */
921 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
[all...] |
| bfin-dis.c | 92 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
456 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf) macro
[all...] |
