| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 93 v64i32 = 44, // 64 x i32 enumerator in enum:llvm::MVT::SimpleValueType
273 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64);
341 case v64i32: return i32;
376 case v64i32: return 64;
503 case v64i32:
623 if (NumElements == 64) return MVT::v64i32;
|
| ValueTypes.td | 70 def v64i32 : ValueType<2048,44>; // 32 x i32 vector value
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonIntrinsicsV60.td | 71 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
72 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
76 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
77 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
[all...] |
| HexagonISelLowering.cpp | 209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
422 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
423 LocVT = MVT::v64i32;
424 ValVT = MVT::v64i32;
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
495 } else if (LocVT == MVT::v64i32) {
548 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 ||
[all...] |
| HexagonInstrInfoVector.td | 86 defm : bitconvert_dblvec128B<v64i32, v128i16>;
90 defm : bitconvert_dblvec128B<v64i32, v256i8>;
|
| HexagonRegisterInfo.td | 229 [v256i8,v128i16,v64i32,v32i64], 2048,
|
| HexagonInstrInfoV60.td | [all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 171 case MVT::v64i32: return "v64i32";
249 case MVT::v64i32: return VectorType::get(Type::getInt32Ty(Context), 64);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 104 case MVT::v64i32: return "MVT::v64i32";
|
| /external/llvm/include/llvm/IR/ |
| Intrinsics.td | 192 def llvm_v64i32_ty : LLVMType<v64i32>; // 64 x i32
|
