Lines Matching defs:in
5 * you may not use this file except in compliance with the License.
10 * Unless required by applicable law or agreed to in writing, software
93 // intrinsic) in an intrinsified call. This will copy the arguments
96 // Note: The actual parameters are required to be in the locations
124 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
161 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
167 __ Mfc1(out_lo, in);
168 __ MoveFromFpuHigh(out_hi, in);
172 __ Mfc1(out, in);
212 Register in = locations->InAt(0).AsRegister<Register>();
214 __ Mtc1(in, out);
258 Register in = locations->InAt(0).AsRegister<Register>();
262 __ Wsbh(out, in);
265 __ Sll(TMP, in, 24);
267 __ Sll(out, in, 16);
272 Register in = locations->InAt(0).AsRegister<Register>();
276 __ Rotr(out, in, 16);
280 // __ Rotr(out, in, 16);
281 __ Sll(TMP, in, 16);
282 __ Srl(out, in, 16);
335 __ Or(TMP, TMP, AT); // Hold in TMP until it's safe
462 Register in = locations->InAt(0).AsRegister<Register>();
465 __ ClzR6(out, in);
467 __ ClzR2(out, in);
496 Register in;
503 // If in_lo is zero then count the number of trailing zeroes in in_hi;
504 // otherwise count the number of trailing zeroes in in_lo.
515 in = out;
517 in = locations->InAt(0).AsRegister<Register>();
519 // Since we only get here in the 32-bit case, this value will never
521 in_lo = in;
528 __ Rotr(out, in, 16);
535 __ Addiu(TMP, in, -1);
536 __ Xor(out, TMP, in);
547 // If in_lo is zero, then we counted the number of trailing zeroes in in_hi so we must add the
548 // number of trailing zeroes in in_lo (32) to get the correct final count
631 // machine instructions each for the values being used in this algorithm).
637 // algorithm the count for a 64-bit operand can be performed in 33
642 Register in = locations->InAt(0).AsRegister<Register>();
644 __ Srl(TMP, in, 1);
647 __ Subu(TMP, in, TMP);
749 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
753 __ AbsD(out, in);
755 __ AbsS(out, in);
784 // The comments in this section show the analogous operations which would
785 // be performed if we had 64-bit registers "in", and "out".
786 // __ Dsra32(AT, in, 31);
788 // __ Xor(out, in, AT);
796 Register in = locations->InAt(0).AsRegister<Register>();
799 __ Sra(AT, in, 31);
800 __ Xor(out, in, AT);
1077 // first input register is needed to make sure that value in the
1079 // computing the output value. The logic in the corresponding else
1081 // register isn't clobbered in the event that it's the same register
1285 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
1288 __ SqrtD(out, in);
1318 // unaligned halfwords so the code loads individual bytes, in case
1411 // unaligned halfwords so the code stores individual bytes, in case
1614 // The "offset" argument is passed as a "long", i.e., it's 64-bits in
1837 // in the case that the store fails. Whether the
1842 // of those two types. It's left here in case the code needs to support
1843 // other types in the future.
1902 // TODO: For simplicity, the index parameter is requested in a
2032 // Assertions that must hold in order to compare strings 2 characters at a time.
2048 // If loop does not result in returning false, we return true.
2087 // fits in a valid 16-bit (MIPS halfword) value. If it doesn't then
2088 // the character being searched for, if it exists in the string, is
2089 // encoded using UTF-16 and stored in the string as two (16-bit)
2268 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
2275 __ ClassD(FTMP, in);
2277 __ ClassS(FTMP, in);
2285 __ MoveFromFpuHigh(TMP, in);
2288 __ Mfc1(TMP, in);
2296 __ Mfc1(AT, in);
2355 Register in = locations->InAt(0).AsRegister<Register>();
2359 __ ClzR6(TMP, in);
2361 __ ClzR2(TMP, in);
2364 __ Srlv(AT, AT, TMP); // Srlv shifts in the range of [0;31] bits (lower 5 bits of arg).
2365 __ And(out, AT, in); // So this is required for 0 (=shift by 32).
2409 Register in = locations->InAt(0).AsRegister<Register>();
2412 __ Subu(TMP, ZERO, in);
2413 __ And(out, TMP, in);
