Lines Matching defs:out
122 Location out = invoke_->GetLocations()->Out();
123 if (out.IsValid()) {
124 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
125 DCHECK(!invoke_->GetLocations()->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
126 MoveFromReturnRegister(out, invoke_->GetType(), codegen);
164 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
165 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
170 Register out = locations->Out().AsRegister<Register>();
172 __ Mfc1(out, in);
203 FRegister out = locations->Out().AsFpuRegister<FRegister>();
209 __ Mtc1(in_lo, out);
210 __ MoveToFpuHigh(in_hi, out);
214 __ Mtc1(in, out);
259 Register out = locations->Out().AsRegister<Register>();
262 __ Wsbh(out, in);
263 __ Seh(out, out);
267 __ Sll(out, in, 16);
268 __ Srl(out, out, 24);
269 __ Or(out, out, TMP);
273 Register out = locations->Out().AsRegister<Register>();
276 __ Rotr(out, in, 16);
277 __ Wsbh(out, out);
280 // __ Rotr(out, in, 16);
282 __ Srl(out, in, 16);
283 __ Or(out, out, TMP);
284 // __ Wsbh(out, out);
286 __ And(TMP, out, AT);
288 __ Srl(out, out, 8);
289 __ And(out, out, AT);
290 __ Or(out, out, TMP);
294 __ Bitswap(out, out);
297 __ And(TMP, out, AT);
299 __ Srl(out, out, 4);
300 __ And(out, out, AT);
301 __ Or(out, TMP, out);
303 __ And(TMP, out, AT);
305 __ Srl(out, out, 2);
306 __ And(out, out, AT);
307 __ Or(out, TMP, out);
309 __ And(TMP, out, AT);
311 __ Srl(out, out, 1);
312 __ And(out, out, AT);
313 __ Or(out, TMP, out);
319 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
320 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
446 Register out = locations->Out().AsRegister<Register>();
460 __ Addu(out, AT, TMP);
465 __ ClzR6(out, in);
467 __ ClzR2(out, in);
494 Register out = locations->Out().AsRegister<Register>();
505 // out = in_lo ? in_lo : in_hi;
507 __ Seleqz(out, in_hi, in_lo);
509 __ Or(out, out, TMP);
511 __ Movz(out, in_hi, in_lo);
512 __ Movn(out, in_lo, in_lo);
515 in = out;
528 __ Rotr(out, in, 16);
529 __ Wsbh(out, out);
530 __ Bitswap(out, out);
531 __ ClzR6(out, out);
536 __ Xor(out, TMP, in);
537 __ And(out, out, TMP);
539 __ ClzR2(out, out);
543 __ Subu(out, TMP, out);
555 __ Addu(out, out, TMP);
617 Register out = locations->Out().AsRegister<Register>();
649 __ And(out, TMP, AT);
652 __ Addu(TMP, out, TMP);
653 __ Srl(out, TMP, 4);
654 __ Addu(out, out, TMP);
656 __ And(out, out, AT);
659 __ MulR6(out, out, TMP);
661 __ MulR2(out, out, TMP);
663 __ Srl(out, out, 24);
671 Register out_lo = out;
720 __ Addu(out, out_hi, out_lo);
750 FRegister out = locations->Out().AsFpuRegister<FRegister>();
753 __ AbsD(out, in);
755 __ AbsS(out, in);
781 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
782 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
785 // be performed if we had 64-bit registers "in", and "out".
788 // __ Xor(out, in, AT);
791 // __ Dsubu(out, out, AT);
797 Register out = locations->Out().AsRegister<Register>();
800 __ Xor(out, in, AT);
801 __ Subu(out, out, AT);
828 FRegister out = locations->Out().AsFpuRegister<FRegister>();
835 FRegister ftmp = ((out != a) && (out != b)) ? out : FTMP;
853 if (ftmp != out) {
854 __ MovD(out, ftmp);
862 __ MinD(out, a, b);
864 __ MaxD(out, a, b);
876 if (ftmp != out) {
877 __ MovS(out, ftmp);
885 __ MinS(out, a, b);
887 __ MaxS(out, a, b);
945 __ Mtc1(AT, out);
946 __ MoveToFpuHigh(TMP, out);
948 __ Mtc1(TMP, out);
975 __ MovtD(out, a);
976 __ MovfD(out, b);
978 __ MovtS(out, a);
979 __ MovfS(out, b);
1090 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
1091 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
1131 Register out = locations->Out().AsRegister<Register>();
1134 if (out != a) {
1135 __ Move(out, a);
1146 __ Or(out, TMP, AT);
1155 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
1156 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
1197 Register out = locations->Out().AsRegister<Register>();
1200 if (out != a) {
1201 __ Move(out, a);
1206 if (out != a) {
1207 __ Movn(out, a, AT);
1209 if (out != b) {
1210 __ Movz(out, b, AT);
1213 if (out != a) {
1214 __ Movz(out, a, AT);
1216 if (out != b) {
1217 __ Movn(out, b, AT);
1286 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1288 __ SqrtD(out, in);
1299 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1301 __ Lb(out, adr, 0);
1312 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1315 __ Lh(out, adr, 0);
1322 __ Lb(out, adr, 0); // This byte can be either sign-extended, or
1325 __ Ins(out, AT, 8, 24);
1330 __ Lb(out, adr, 1); // This byte must be sign-extended.
1331 __ Sll(out, out, 8);
1332 __ Or(out, out, AT);
1344 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1347 __ Lw(out, adr, 0);
1349 __ Lwr(out, adr, 0);
1350 __ Lwl(out, adr, 3);
1362 Register out_lo = invoke->GetLocations()->Out().AsRegisterPairLow<Register>();
1363 Register out_hi = invoke->GetLocations()->Out().AsRegisterPairHigh<Register>();
1469 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1472 out,
1514 Register trg_lo = locations->Out().AsRegisterPairLow<Register>();
1515 Register trg_hi = locations->Out().AsRegisterPairHigh<Register>();
1527 Register trg = locations->Out().AsRegister<Register>();
1802 Register out = locations->Out().AsRegister<Register>();
1804 DCHECK_NE(base, out);
1805 DCHECK_NE(offset_lo, out);
1806 DCHECK_NE(expected, out);
1824 __ LlR6(out, TMP);
1826 __ LlR2(out, TMP);
1832 __ Subu(out, out, expected); // If we didn't get the 'expected'
1833 __ Sltiu(out, out, 1); // value, set 'out' to false, and
1834 __ Beqz(out, &exit_loop); // return.
1835 __ Move(out, value); // Use 'out' for the 'store conditional' instruction.
1839 // correct boolean value into the 'out' register.
1846 __ ScR6(out, TMP);
1848 __ ScR2(out, TMP);
1851 __ Beqz(out, &loop_head); // If we couldn't do the read-modify-write
1898 Register out = locations->Out().AsRegister<Register>();
1915 // out = obj[2*idx].
1918 __ Lhu(out, TMP, value_offset); // Load char at location idx
1978 Register out = locations->Out().AsRegister<Register>();
2002 __ LoadConst32(out, 1);
2039 __ Lw(out, TMP, value_offset);
2041 __ Bne(out, temp2, &return_false);
2050 __ LoadConst32(out, 1);
2055 __ LoadConst32(out, 0);
2269 Register out = locations->Out().AsRegister<Register>();
2279 __ Mfc1(out, FTMP);
2280 __ Andi(out, out, kPositiveInfinity | kNegativeInfinity);
2281 __ Sltu(out, ZERO, out);
2300 __ Sltiu(out, TMP, 1);
2331 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
2332 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
2356 Register out = locations->Out().AsRegister<Register>();
2365 __ And(out, AT, in); // So this is required for 0 (=shift by 32).
2396 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
2397 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
2410 Register out = locations->Out().AsRegister<Register>();
2413 __ And(out, TMP, in);
