Lines Matching full:immediate
509 bool Thumb2Assembler::ShifterOperandCanAlwaysHold(uint32_t immediate) {
510 return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
516 uint32_t immediate,
520 shifter_op->immed_ = immediate;
527 if (immediate < (1 << 12) && set_cc != kCcSet) {
530 return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
534 return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
538 return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
1185 // Check special case for SP relative ADD and SUB immediate.
1187 // If the immediate is in range, use 16 bit.
1189 if (so.GetImmediate() < (1 << 9)) { // 9 bit immediate.
1193 if (so.GetImmediate() < (1 << 10)) { // 10 bit immediate.
1216 // immediate variants.
1255 // The only thumb1 instructions with a register and an immediate are ADD and SUB
1256 // with a 3-bit immediate, and RSB with zero immediate.
1268 // ADD, SUB, CMP and MOV may be thumb1 only if the immediate is 8 bits.
1274 // For ADD and SUB allow also negative 8-bit immediate as we will emit the oposite opcode.
1288 // Check for MOV with an ROR/RRX. There is no 16-bit ROR immediate and no 16-bit RRX.
1399 // Modified immediate.
1402 LOG(FATAL) << "Immediate value cannot fit in thumb2 modified immediate";
1443 uint8_t immediate = 0;
1451 immediate = so.GetImmediate();
1458 immediate, 31u);
1462 DCHECK(1 <= immediate && immediate <= 32);
1463 immediate &= 31; // 32 is encoded as 0.
1467 DCHECK(1 <= immediate && immediate <= 32);
1468 immediate &= 31; // 32 is encoded as 0.
1471 case ROR: // No 16-bit ROR immediate.
1480 immediate = so.GetImmediate();
1609 (use_immediate ? (immediate << immediate_shift) : 0);
1628 uint32_t immediate = 0; // Should be at most 10 bits but keep the full immediate for CHECKs.
1633 immediate = so.GetImmediate();
1634 if (!IsUint<10>(immediate)) {
1637 immediate = -immediate;
1638 DCHECK(IsUint<10>(immediate)); // More stringent checks below.
1665 immediate = static_cast<uint32_t>(so.GetRegister());
1670 // Immediate.
1676 CHECK(IsUint<9>(immediate));
1677 CHECK_ALIGNED(immediate, 4);
1684 immediate >>= 2;
1690 CHECK(IsUint<10>(immediate));
1691 CHECK_ALIGNED(immediate, 4);
1697 immediate >>= 2;
1700 CHECK(IsUint<3>(immediate));
1706 CHECK(IsUint<8>(immediate));
1727 immediate = static_cast<uint32_t>(rm);
1736 CHECK(IsUint<9>(immediate));
1737 CHECK_ALIGNED(immediate, 4);
1744 immediate >>= 2;
1747 CHECK(IsUint<3>(immediate));
1753 CHECK(IsUint<8>(immediate));
1770 (use_immediate ? (immediate << immediate_shift) : 0);
2312 // NOTE: this only support immediate offsets, not [rx,ry].
2338 // Immediate offset
3396 imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate.
3405 imm32 = (imm32 << 11) >> 11; // sign extend 21 bit immediate.
