Lines Matching full:static_cast
96 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
97 static_cast<uint32_t>(rs) << kRsShift |
98 static_cast<uint32_t>(rt) << kRtShift |
99 static_cast<uint32_t>(rd) << kRdShift |
109 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
110 static_cast<uint32_t>(rs) << kRsShift |
111 static_cast<uint32_t>(ZERO) << kRtShift |
112 static_cast<uint32_t>(rd) << kRdShift |
122 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
123 static_cast<uint32_t>(ZERO) << kRsShift |
124 static_cast<uint32_t>(rt) << kRtShift |
125 static_cast<uint32_t>(rd) << kRdShift |
134 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
135 static_cast<uint32_t>(rs) << kRsShift |
136 static_cast<uint32_t>(rt) << kRtShift |
144 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
145 static_cast<uint32_t>(rs) << kRsShift |
152 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift | imm26;
161 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
163 static_cast<uint32_t>(ft) << kFtShift |
164 static_cast<uint32_t>(fs) << kFsShift |
165 static_cast<uint32_t>(fd) << kFdShift |
172 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
174 static_cast<uint32_t>(ft) << kFtShift |
288 EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);
292 EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);
306 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size - 1), pos, 0x3);
313 EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos - 32, 0x6);
341 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
345 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
349 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02);
353 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
373 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);
377 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);
381 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a);
385 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);
389 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);
393 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);
397 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e);
401 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);
449 EmitI(0xf, static_cast<GpuRegister>(0), rt, imm16);
453 EmitI(1, rs, static_cast<GpuRegister>(6), imm16);
457 EmitI(1, rs, static_cast<GpuRegister>(0x1e), imm16);
461 EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),
462 static_cast<GpuRegister>(0), stype & 0x1f, 0xf);
522 EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);
534 EmitI(0x3B, rs, static_cast<GpuRegister>(0x1E), imm16);
547 EmitI(0x36, static_cast<GpuRegister>(0), rt, imm16);
551 EmitI(0x3E, static_cast<GpuRegister>(0), rt, imm16);
568 EmitI(0x17, static_cast<GpuRegister>(0), rt, imm16);
585 EmitI(0x16, static_cast<GpuRegister>(0), rt, imm16);
689 Bc1eqz(static_cast<FpuRegister>(rs), imm16_21);
693 Bc1nez(static_cast<FpuRegister>(rs), imm16_21);
734 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x4);
738 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x4);
742 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x5);
746 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x5);
750 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);
754 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x6);
758 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x7);
762 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);
766 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x8);
770 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x8);
774 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xc);
778 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xc);
782 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x9);
786 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x9);
790 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xd);
794 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xd);
798 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xa);
802 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xa);
806 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xe);
810 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xe);
814 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xb);
818 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xb);
822 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xf);
826 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xf);
838 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1a);
842 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1a);
846 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1b);
850 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1b);
950 EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);
954 EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x21);
958 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x20);
962 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
966 EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x20);
970 EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x21);
974 EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
978 EmitFR(0x11, 0x03, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
982 EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
986 EmitFR(0x11, 0x07, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
990 EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
994 EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
998 EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16);
1002 EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16);
1006 EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16);
1010 EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16);
1014 EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),
1015 static_cast<GpuRegister>(0), 0, 0xD);
1019 EmitR(0x0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),
1020 static_cast<GpuRegister>(0), 0, 0x0);
1418 int64_t distance = static_cast<int64_t>(target) - location;
1487 int64_t distance = static_cast<int64_t>(target_) - location_;
1736 CHECK_LT(branch->GetSize(), static_cast<uint32_t>(Branch::kMaxBranchSize));
1796 Bcond(label, kCondF, static_cast<GpuRegister>(ft), ZERO);
1800 Bcond(label, kCondT, static_cast<GpuRegister>(ft), ZERO);
1807 !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) {
1852 !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) {
1910 !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) {
1947 !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) {
1975 return dwarf::Reg::Mips64Core(static_cast<int>(reg));
2056 Daddiu64(SP, SP, static_cast<int32_t>(-adjust));
2063 Daddiu64(SP, SP, static_cast<int32_t>(adjust));
