Lines Matching refs:fs
156 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
159 CHECK_NE(fs, kNoFpuRegister);
164 static_cast<uint32_t>(fs) << kFsShift |
701 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
702 EmitFR(0x11, 0x10, ft, fs, fd, 0x0);
705 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
706 EmitFR(0x11, 0x10, ft, fs, fd, 0x1);
709 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
710 EmitFR(0x11, 0x10, ft, fs, fd, 0x2);
713 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
714 EmitFR(0x11, 0x10, ft, fs, fd, 0x3);
717 void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
718 EmitFR(0x11, 0x11, ft, fs, fd, 0x0);
721 void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
722 EmitFR(0x11, 0x11, ft, fs, fd, 0x1);
725 void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
726 EmitFR(0x11, 0x11, ft, fs, fd, 0x2);
729 void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
730 EmitFR(0x11, 0x11, ft, fs, fd, 0x3);
733 void Mips64Assembler::SqrtS(FpuRegister fd, FpuRegister fs) {
734 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x4);
737 void Mips64Assembler::SqrtD(FpuRegister fd, FpuRegister fs) {
738 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x4);
741 void Mips64Assembler::AbsS(FpuRegister fd, FpuRegister fs) {
742 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x5);
745 void Mips64Assembler::AbsD(FpuRegister fd, FpuRegister fs) {
746 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x5);
749 void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) {
750 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);
753 void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) {
754 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x6);
757 void Mips64Assembler::NegS(FpuRegister fd, FpuRegister fs) {
758 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x7);
761 void Mips64Assembler::NegD(FpuRegister fd, FpuRegister fs) {
762 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);
765 void Mips64Assembler::RoundLS(FpuRegister fd, FpuRegister fs) {
766 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x8);
769 void Mips64Assembler::RoundLD(FpuRegister fd, FpuRegister fs) {
770 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x8);
773 void Mips64Assembler::RoundWS(FpuRegister fd, FpuRegister fs) {
774 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xc);
777 void Mips64Assembler::RoundWD(FpuRegister fd, FpuRegister fs) {
778 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xc);
781 void Mips64Assembler::TruncLS(FpuRegister fd, FpuRegister fs) {
782 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x9);
785 void Mips64Assembler::TruncLD(FpuRegister fd, FpuRegister fs) {
786 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x9);
789 void Mips64Assembler::TruncWS(FpuRegister fd, FpuRegister fs) {
790 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xd);
793 void Mips64Assembler::TruncWD(FpuRegister fd, FpuRegister fs) {
794 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xd);
797 void Mips64Assembler::CeilLS(FpuRegister fd, FpuRegister fs) {
798 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xa);
801 void Mips64Assembler::CeilLD(FpuRegister fd, FpuRegister fs) {
802 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xa);
805 void Mips64Assembler::CeilWS(FpuRegister fd, FpuRegister fs) {
806 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xe);
809 void Mips64Assembler::CeilWD(FpuRegister fd, FpuRegister fs) {
810 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xe);
813 void Mips64Assembler::FloorLS(FpuRegister fd, FpuRegister fs) {
814 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xb);
817 void Mips64Assembler::FloorLD(FpuRegister fd, FpuRegister fs) {
818 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xb);
821 void Mips64Assembler::FloorWS(FpuRegister fd, FpuRegister fs) {
822 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xf);
825 void Mips64Assembler::FloorWD(FpuRegister fd, FpuRegister fs) {
826 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xf);
829 void Mips64Assembler::SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
830 EmitFR(0x11, 0x10, ft, fs, fd, 0x10);
833 void Mips64Assembler::SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
834 EmitFR(0x11, 0x11, ft, fs, fd, 0x10);
837 void Mips64Assembler::RintS(FpuRegister fd, FpuRegister fs) {
838 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1a);
841 void Mips64Assembler::RintD(FpuRegister fd, FpuRegister fs) {
842 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1a);
845 void Mips64Assembler::ClassS(FpuRegister fd, FpuRegister fs) {
846 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1b);
849 void Mips64Assembler::ClassD(FpuRegister fd, FpuRegister fs) {
850 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1b);
853 void Mips64Assembler::MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
854 EmitFR(0x11, 0x10, ft, fs, fd, 0x1c);
857 void Mips64Assembler::MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
858 EmitFR(0x11, 0x11, ft, fs, fd, 0x1c);
861 void Mips64Assembler::MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
862 EmitFR(0x11, 0x10, ft, fs, fd, 0x1e);
865 void Mips64Assembler::MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
866 EmitFR(0x11, 0x11, ft, fs, fd, 0x1e);
869 void Mips64Assembler::CmpUnS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
870 EmitFR(0x11, 0x14, ft, fs, fd, 0x01);
873 void Mips64Assembler::CmpEqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
874 EmitFR(0x11, 0x14, ft, fs, fd, 0x02);
877 void Mips64Assembler::CmpUeqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
878 EmitFR(0x11, 0x14, ft, fs, fd, 0x03);
881 void Mips64Assembler::CmpLtS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
882 EmitFR(0x11, 0x14, ft, fs, fd, 0x04);
885 void Mips64Assembler::CmpUltS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
886 EmitFR(0x11, 0x14, ft, fs, fd, 0x05);
889 void Mips64Assembler::CmpLeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
890 EmitFR(0x11, 0x14, ft, fs, fd, 0x06);
893 void Mips64Assembler::CmpUleS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
894 EmitFR(0x11, 0x14, ft, fs, fd, 0x07);
897 void Mips64Assembler::CmpOrS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
898 EmitFR(0x11, 0x14, ft, fs, fd, 0x11);
901 void Mips64Assembler::CmpUneS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
902 EmitFR(0x11, 0x14, ft, fs, fd, 0x12);
905 void Mips64Assembler::CmpNeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
906 EmitFR(0x11, 0x14, ft, fs, fd, 0x13);
909 void Mips64Assembler::CmpUnD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
910 EmitFR(0x11, 0x15, ft, fs, fd, 0x01);
913 void Mips64Assembler::CmpEqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
914 EmitFR(0x11, 0x15, ft, fs, fd, 0x02);
917 void Mips64Assembler::CmpUeqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
918 EmitFR(0x11, 0x15, ft, fs, fd, 0x03);
921 void Mips64Assembler::CmpLtD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
922 EmitFR(0x11, 0x15, ft, fs, fd, 0x04);
925 void Mips64Assembler::CmpUltD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
926 EmitFR(0x11, 0x15, ft, fs, fd, 0x05);
929 void Mips64Assembler::CmpLeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
930 EmitFR(0x11, 0x15, ft, fs, fd, 0x06);
933 void Mips64Assembler::CmpUleD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
934 EmitFR(0x11, 0x15, ft, fs, fd, 0x07);
937 void Mips64Assembler::CmpOrD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
938 EmitFR(0x11, 0x15, ft, fs, fd, 0x11);
941 void Mips64Assembler::CmpUneD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
942 EmitFR(0x11, 0x15, ft, fs, fd, 0x12);
945 void Mips64Assembler::CmpNeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
946 EmitFR(0x11, 0x15, ft, fs, fd, 0x13);
949 void Mips64Assembler::Cvtsw(FpuRegister fd, FpuRegister fs) {
950 EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);
953 void Mips64Assembler::Cvtdw(FpuRegister fd, FpuRegister fs) {
954 EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x21);
957 void Mips64Assembler::Cvtsd(FpuRegister fd, FpuRegister fs) {
958 EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x20);
961 void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {
962 EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
965 void Mips64Assembler::Cvtsl(FpuRegister fd, FpuRegister fs) {
966 EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x20);
969 void Mips64Assembler::Cvtdl(FpuRegister fd, FpuRegister fs) {
970 EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x21);
973 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) {
974 EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
977 void Mips64Assembler::Mfhc1(GpuRegister rt, FpuRegister fs) {
978 EmitFR(0x11, 0x03, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
981 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) {
982 EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
985 void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) {
986 EmitFR(0x11, 0x07, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
989 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) {
990 EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
993 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) {
994 EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
