Lines Matching full:immediate
78 void X86_64Assembler::pushq(const Immediate& imm) {
80 CHECK(imm.is_int32()); // pushq only supports 32b immediate.
106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) {
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) {
131 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) {
189 void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
292 void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
352 void X86_64Assembler::movw(const Address& dst, const Immediate& imm) {
929 void X86_64Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
941 void X86_64Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1132 void X86_64Assembler::ffree(const Immediate& index) {
1227 void X86_64Assembler::cmpw(const Address& address, const Immediate& imm) {
1236 void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) {
1268 Immediate& imm) {
1284 void X86_64Assembler::cmpq(CpuRegister reg, const Immediate& imm) {
1286 CHECK(imm.is_int32()); // cmpq only supports 32b immediate.
1300 void X86_64Assembler::cmpq(const Address& address, const Immediate& imm) {
1301 CHECK(imm.is_int32()); // cmpq only supports 32b immediate.
1340 void X86_64Assembler::testl(CpuRegister reg, const Immediate& immediate) {
1344 if (immediate.is_uint8() && reg.AsRegister() < 4) {
1345 // Use zero-extended 8-bit immediate.
1352 EmitUint8(immediate.value() & 0xFF);
1356 EmitImmediate(immediate);
1361 EmitImmediate(immediate);
1398 void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) {
1405 void X86_64Assembler::andq(CpuRegister reg, const Immediate& imm) {
1407 CHECK(imm.is_int32()); // andq only supports 32b immediate.
1445 void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) {
1452 void X86_64Assembler::orq(CpuRegister dst, const Immediate& imm) {
1454 CHECK(imm.is_int32()); // orq only supports 32b immediate.
1492 void X86_64Assembler::xorl(CpuRegister dst, const Immediate& imm) {
1507 void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) {
1509 CHECK(imm.is_int32()); // xorq only supports 32b immediate.
1575 void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) {
1582 void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) {
1584 CHECK(imm.is_int32()); // addq only supports 32b immediate.
1615 void X86_64Assembler::addl(const Address& address, const Immediate& imm) {
1630 void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) {
1637 void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) {
1639 CHECK(imm.is_int32()); // subq only supports 32b immediate.
1706 void X86_64Assembler::imull(CpuRegister dst, CpuRegister src, const Immediate& imm) {
1708 CHECK(imm.is_int32()); // imull only supports 32b immediate.
1720 // Not representable, use full immediate.
1728 void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) {
1751 void X86_64Assembler::imulq(CpuRegister reg, const Immediate& imm) {
1755 void X86_64Assembler::imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) {
1757 CHECK(imm.is_int32()); // imulq only supports 32b immediate.
1769 // Not representable, use full immediate.
1825 void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) {
1830 void X86_64Assembler::shlq(CpuRegister reg, const Immediate& imm) {
1845 void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) {
1850 void X86_64Assembler::shrq(CpuRegister reg, const Immediate& imm) {
1865 void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) {
1875 void X86_64Assembler::sarq(CpuRegister reg, const Immediate& imm) {
1885 void X86_64Assembler::roll(CpuRegister reg, const Immediate& imm) {
1895 void X86_64Assembler::rorl(CpuRegister reg, const Immediate& imm) {
1905 void X86_64Assembler::rolq(CpuRegister reg, const Immediate& imm) {
1915 void X86_64Assembler::rorq(CpuRegister reg, const Immediate& imm) {
1957 void X86_64Assembler::enter(const Immediate& imm) {
1979 void X86_64Assembler::ret(const Immediate& imm) {
2162 void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) {
2168 subl(reg, Immediate(value));
2333 pushq(Immediate(High32Bits(constant)));
2334 pushq(Immediate(Low32Bits(constant)));
2336 addq(CpuRegister(RSP), Immediate(2 * sizeof(intptr_t)));
2396 void X86_64Assembler::EmitImmediate(const Immediate& imm) {
2407 const Immediate& immediate) {
2410 if (immediate.is_int8()) {
2411 // Use sign-extended 8-bit immediate.
2414 EmitUint8(immediate.value() & 0xFF);
2418 EmitImmediate(immediate);
2422 EmitImmediate(immediate);
2464 const Immediate& imm) {
2661 subq(CpuRegister(RSP), Immediate(rest_of_frame));
2718 addq(CpuRegister(RSP), Immediate(adjust));
2736 addq(CpuRegister(RSP), Immediate(-static_cast<int64_t>(adjust)));
2742 addq(CpuRegister(RSP), Immediate(adjust));
2793 movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
2798 gs()->movl(Address::Absolute(dest, true), Immediate(imm)); // TODO(64) movq?
2936 subl(CpuRegister(RSP), Immediate(16));
2946 addq(CpuRegister(RSP), Immediate(16));
3149 gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0));
