Lines Matching full:trigger
53 * Note: The FIFO trigger levels are chip specific:
75 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
76 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
77 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
78 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
79 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
81 #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
82 #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
83 #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
84 #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
85 #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
86 #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
87 #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
88 #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
186 #define UART_TI752_TLR 7 /* I/O: trigger level register */
193 * Out: Fifo custom trigger levels */
195 * These are the definitions for the Programmable Trigger Register
214 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
215 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
216 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
217 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
219 #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
220 #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
257 #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
258 #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
275 #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
371 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
372 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
373 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
374 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
376 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
377 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
