Lines Matching defs:gb_tile_mode
1065 static void si_gb_tile_mode(uint32_t gb_tile_mode,
1074 switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
1097 switch (SI__GB_TILE_MODE__NUM_BANKS(gb_tile_mode)) {
1114 switch (SI__GB_TILE_MODE__MACRO_TILE_ASPECT(gb_tile_mode)) {
1131 switch (SI__GB_TILE_MODE__BANK_WIDTH(gb_tile_mode)) {
1148 switch (SI__GB_TILE_MODE__BANK_HEIGHT(gb_tile_mode)) {
1165 switch (SI__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) {
1283 uint32_t gb_tile_mode;
1340 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode];
1341 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split);
1391 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
1392 si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_split);
1699 uint32_t gb_tile_mode;
1703 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1704 si_gb_tile_mode(gb_tile_mode, &num_pipes, &num_banks, NULL, NULL, NULL, NULL);
1860 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1867 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
1893 switch (CIK__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) {
1917 switch (CIK__GB_TILE_MODE__SAMPLE_SPLIT(gb_tile_mode)) {
