Lines Matching refs:stencil_tile_split
822 surf->stencil_tile_split, surf->bo_size, 0);
958 surf->stencil_tile_split = 64;
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
1317 surf->stencil_tile_split = 64;
1341 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split);
1712 r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, surf->stencil_tile_split, surf->bo_size, 0);
2145 surf->stencil_tile_split = 64;
2171 &surf->stencil_tile_split,
2315 surf->stencil_tile_split, num_pipes, num_banks,
