Lines Matching refs:v12
245 ld1 {v12.4h},[x0],x6
268 smlal v20.4s, v12.4h, v1.h[0]
270 smlal v22.4s, v12.4h, v3.h[0]
272 smlal v16.4s, v12.4h, v5.h[0]
274 smlal v18.4s, v12.4h, v7.h[0]
317 ld1 {v12.4h},[x0],x6
342 smlal v20.4s, v12.4h, v3.h[0]
344 smlsl v22.4s, v12.4h, v7.h[0]
346 smlsl v16.4s, v12.4h, v1.h[0]
348 smlsl v18.4s, v12.4h, v5.h[0]
391 ld1 {v12.4h},[x0],x6
411 smlal v20.4s, v12.4h, v5.h[0]
413 smlsl v22.4s, v12.4h, v1.h[0]
415 smlal v16.4s, v12.4h, v7.h[0]
417 smlal v18.4s, v12.4h, v3.h[0]
459 ld1 {v12.4h},[x0],x6
477 smlal v20.4s, v12.4h, v7.h[0]
479 smlsl v22.4s, v12.4h, v5.h[0]
481 smlal v16.4s, v12.4h, v3.h[0]
483 smlsl v18.4s, v12.4h, v1.h[0]
492 add v12.4s, v22.4s , v26.4s
507 sqrshrn v12.4h, v12.4s,#shift_stage1_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
520 trn1 v24.4h, v30.4h, v12.4h
521 trn2 v25.4h, v30.4h, v12.4h
527 trn1 v12.2s, v25.2s, v27.2s
557 st1 { v12.4h, v13.4h},[x1],#16
606 ld1 {v12.4h},[x0],x6
624 smlsl v20.4s, v12.4h, v7.h[0]
626 smlsl v22.4s, v12.4h, v5.h[0]
628 smlsl v16.4s, v12.4h, v3.h[0]
630 smlsl v18.4s, v12.4h, v1.h[0]
679 ld1 {v12.4h},[x0],x6
700 smlal v20.4s, v12.4h, v5.h[0]
702 smlal v22.4s, v12.4h, v1.h[0]
704 smlal v16.4s, v12.4h, v7.h[0]
706 smlsl v18.4s, v12.4h, v3.h[0]
754 ld1 {v12.4h},[x0],x6
772 smlsl v20.4s, v12.4h, v3.h[0]
774 smlsl v22.4s, v12.4h, v7.h[0]
776 smlal v16.4s, v12.4h, v1.h[0]
778 smlsl v18.4s, v12.4h, v5.h[0]
817 ld1 {v12.4h},[x0],x6
838 smlal v20.4s, v12.4h, v1.h[0]
840 smlsl v22.4s, v12.4h, v3.h[0]
842 smlal v16.4s, v12.4h, v5.h[0]
844 smlsl v18.4s, v12.4h, v7.h[0]
851 add v12.4s, v22.4s , v26.4s
866 sqrshrn v12.4h, v12.4s,#shift_stage1_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
876 trn1 v24.4h, v30.4h, v12.4h
877 trn2 v25.4h, v30.4h, v12.4h
883 trn1 v12.2s, v25.2s, v27.2s
902 st1 { v12.4h, v13.4h},[x1],#16
947 ld1 {v12.4h},[x0],x6
967 smlsl v20.4s, v12.4h, v1.h[0]
969 smlsl v22.4s, v12.4h, v3.h[0]
971 smlsl v16.4s, v12.4h, v5.h[0]
973 smlsl v18.4s, v12.4h, v7.h[0]
1015 ld1 {v12.4h},[x0],x6
1037 smlsl v20.4s, v12.4h, v3.h[0]
1039 smlal v22.4s, v12.4h, v7.h[0]
1041 smlal v16.4s, v12.4h, v1.h[0]
1043 smlal v18.4s, v12.4h, v5.h[0]
1085 ld1 {v12.4h},[x0],x6
1104 smlsl v20.4s, v12.4h, v5.h[0]
1106 smlal v22.4s, v12.4h, v1.h[0]
1108 smlsl v16.4s, v12.4h, v7.h[0]
1110 smlsl v18.4s, v12.4h, v3.h[0]
1151 ld1 {v12.4h},[x0],x6
1168 smlsl v20.4s, v12.4h, v7.h[0]
1170 smlal v22.4s, v12.4h, v5.h[0]
1172 smlsl v16.4s, v12.4h, v3.h[0]
1174 smlal v18.4s, v12.4h, v1.h[0]
1181 add v12.4s, v22.4s , v26.4s
1196 sqrshrn v12.4h, v12.4s,#shift_stage1_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
1206 trn1 v24.4h, v30.4h, v12.4h
1207 trn2 v25.4h, v30.4h, v12.4h
1213 trn1 v12.2s, v25.2s, v27.2s
1231 st1 { v12.4h, v13.4h},[x1],#16
1277 ld1 {v12.4h},[x0],x6
1299 smlal v20.4s, v12.4h, v7.h[0]
1301 smlal v22.4s, v12.4h, v5.h[0]
1303 smlal v16.4s, v12.4h, v3.h[0]
1305 smlal v18.4s, v12.4h, v1.h[0]
1349 ld1 {v12.4h},[x0],x6
1371 smlsl v20.4s, v12.4h, v5.h[0]
1373 smlsl v22.4s, v12.4h, v1.h[0]
1375 smlsl v16.4s, v12.4h, v7.h[0]
1377 smlal v18.4s, v12.4h, v3.h[0]
1420 ld1 {v12.4h},[x0],x6
1442 smlal v20.4s, v12.4h, v3.h[0]
1444 smlal v22.4s, v12.4h, v7.h[0]
1446 smlsl v16.4s, v12.4h, v1.h[0]
1448 smlal v18.4s, v12.4h, v5.h[0]
1489 ld1 {v12.4h},[x0],x6
1509 smlsl v20.4s, v12.4h, v1.h[0]
1511 smlal v22.4s, v12.4h, v3.h[0]
1513 smlsl v16.4s, v12.4h, v5.h[0]
1515 smlal v18.4s, v12.4h, v7.h[0]
1522 add v12.4s, v22.4s , v26.4s
1537 sqrshrn v12.4h, v12.4s,#shift_stage1_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
1547 trn1 v24.4h, v30.4h, v12.4h
1548 trn2 v25.4h, v30.4h, v12.4h
1554 trn1 v12.2s, v25.2s, v27.2s
1573 st1 { v12.4h, v13.4h},[x1],#16
1648 ld1 {v12.4h, v13.4h},[x1],#16
1668 smlal v20.4s, v12.4h, v1.h[0]
1670 smlal v22.4s, v12.4h, v3.h[0]
1672 smlal v16.4s, v12.4h, v5.h[0]
1674 smlal v18.4s, v12.4h, v7.h[0]
1713 ld1 {v12.4h, v13.4h},[x1],#16
1732 smlal v20.4s, v12.4h, v3.h[0]
1734 smlsl v22.4s, v12.4h, v7.h[0]
1736 smlsl v16.4s, v12.4h, v1.h[0]
1738 smlsl v18.4s, v12.4h, v5.h[0]
1776 ld1 {v12.4h, v13.4h},[x1],#16
1795 smlal v20.4s, v12.4h, v5.h[0]
1797 smlsl v22.4s, v12.4h, v1.h[0]
1799 smlal v16.4s, v12.4h, v7.h[0]
1801 smlal v18.4s, v12.4h, v3.h[0]
1838 ld1 {v12.4h, v13.4h},[x1],#16
1853 smlal v20.4s, v12.4h, v7.h[0]
1855 smlsl v22.4s, v12.4h, v5.h[0]
1857 smlal v16.4s, v12.4h, v3.h[0]
1859 smlsl v18.4s, v12.4h, v1.h[0]
1866 add v12.4s, v22.4s , v26.4s
1881 sqrshrn v12.4h, v12.4s,#shift_stage2_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage2_idct)
1892 trn1 v24.4h, v30.4h, v12.4h
1893 trn2 v25.4h, v30.4h, v12.4h
1899 trn1 v12.2s, v25.2s, v27.2s
1918 st1 { v12.4h, v13.4h},[x0],#16
1963 ld1 {v12.4h, v13.4h},[x1],#16
1979 smlsl v20.4s, v12.4h, v7.h[0]
1981 smlsl v22.4s, v12.4h, v5.h[0]
1983 smlsl v16.4s, v12.4h, v3.h[0]
1985 smlsl v18.4s, v12.4h, v1.h[0]
2029 ld1 {v12.4h, v13.4h},[x1],#16
2049 smlal v20.4s, v12.4h, v5.h[0]
2051 smlal v22.4s, v12.4h, v1.h[0]
2053 smlal v16.4s, v12.4h, v7.h[0]
2055 smlsl v18.4s, v12.4h, v3.h[0]
2094 ld1 {v12.4h, v13.4h},[x1],#16
2112 smlsl v20.4s, v12.4h, v3.h[0]
2114 smlsl v22.4s, v12.4h, v7.h[0]
2116 smlal v16.4s, v12.4h, v1.h[0]
2118 smlsl v18.4s, v12.4h, v5.h[0]
2154 ld1 {v12.4h, v13.4h},[x1],#16
2171 smlal v20.4s, v12.4h, v1.h[0]
2173 smlsl v22.4s, v12.4h, v3.h[0]
2175 smlal v16.4s, v12.4h, v5.h[0]
2177 smlsl v18.4s, v12.4h, v7.h[0]
2184 add v12.4s, v22.4s , v26.4s
2199 sqrshrn v12.4h, v12.4s,#shift_stage2_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage2_idct)
2209 trn1 v24.4h, v30.4h, v12.4h
2210 trn2 v25.4h, v30.4h, v12.4h
2216 trn1 v12.2s, v25.2s, v27.2s
2235 st1 { v12.4h, v13.4h},[x0],#16
2278 ld1 {v12.4h, v13.4h},[x1],#16
2293 smlsl v20.4s, v12.4h, v1.h[0]
2295 smlsl v22.4s, v12.4h, v3.h[0]
2297 smlsl v16.4s, v12.4h, v5.h[0]
2299 smlsl v18.4s, v12.4h, v7.h[0]
2340 ld1 {v12.4h, v13.4h},[x1],#16
2359 smlsl v20.4s, v12.4h, v3.h[0]
2361 smlal v22.4s, v12.4h, v7.h[0]
2363 smlal v16.4s, v12.4h, v1.h[0]
2365 smlal v18.4s, v12.4h, v5.h[0]
2403 ld1 {v12.4h, v13.4h},[x1],#16
2421 smlsl v20.4s, v12.4h, v5.h[0]
2423 smlal v22.4s, v12.4h, v1.h[0]
2425 smlsl v16.4s, v12.4h, v7.h[0]
2427 smlsl v18.4s, v12.4h, v3.h[0]
2462 ld1 {v12.4h, v13.4h},[x1],#16
2479 smlsl v20.4s, v12.4h, v7.h[0]
2481 smlal v22.4s, v12.4h, v5.h[0]
2483 smlsl v16.4s, v12.4h, v3.h[0]
2485 smlal v18.4s, v12.4h, v1.h[0]
2492 add v12.4s, v22.4s , v26.4s
2507 sqrshrn v12.4h, v12.4s,#shift_stage2_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage2_idct)
2517 trn1 v24.4h, v30.4h, v12.4h
2518 trn2 v25.4h, v30.4h, v12.4h
2524 trn1 v12.2s, v25.2s, v27.2s
2543 st1 { v12.4h, v13.4h},[x0],#16
2587 ld1 {v12.4h, v13.4h},[x1],#16
2607 smlal v20.4s, v12.4h, v7.h[0]
2609 smlal v22.4s, v12.4h, v5.h[0]
2611 smlal v16.4s, v12.4h, v3.h[0]
2613 smlal v18.4s, v12.4h, v1.h[0]
2655 ld1 {v12.4h, v13.4h},[x1],#16
2675 smlsl v20.4s, v12.4h, v5.h[0]
2677 smlsl v22.4s, v12.4h, v1.h[0]
2679 smlsl v16.4s, v12.4h, v7.h[0]
2681 smlal v18.4s, v12.4h, v3.h[0]
2719 ld1 {v12.4h, v13.4h},[x1],#16
2737 smlal v20.4s, v12.4h, v3.h[0]
2739 smlal v22.4s, v12.4h, v7.h[0]
2741 smlsl v16.4s, v12.4h, v1.h[0]
2743 smlal v18.4s, v12.4h, v5.h[0]
2781 ld1 {v12.4h, v13.4h},[x1],#16
2798 smlsl v20.4s, v12.4h, v1.h[0]
2800 smlal v22.4s, v12.4h, v3.h[0]
2802 smlsl v16.4s, v12.4h, v5.h[0]
2804 smlal v18.4s, v12.4h, v7.h[0]
2811 add v12.4s, v22.4s , v26.4s
2826 sqrshrn v12.4h, v12.4s,#shift_stage2_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage2_idct)
2838 trn1 v24.4h, v30.4h, v12.4h
2839 trn2 v25.4h, v30.4h, v12.4h
2845 trn1 v12.2s, v25.2s, v27.2s
2864 st1 { v12.4h, v13.4h},[x0],#16
2875 ld1 {v12.8h},[x0],#16
2917 // swapping v12 upper and v16 lower 64bits
2918 mov v13.d[0], v12.d[1]
2919 mov v12.d[1], v16.d[0]
2941 uaddw v12.8h, v12.8h , v8.8b
2951 sqxtun v12.8b, v12.8h
2961 st1 {v12.8b, v13.8b},[x3],x7
2970 ld1 {v12.8h},[x0],#16
2992 // swapping v12 upper and v16 lower 64bits
2993 mov v13.d[0], v12.d[1]
2994 mov v12.d[1], v16.d[0]
3016 uaddw v12.8h, v12.8h , v8.8b
3026 sqxtun v12.8b, v12.8h
3036 st1 {v12.8b, v13.8b},[x3],x7
