Lines Matching refs:v12
263 st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
306 st1 {v12.4h, v13.4h, v14.4h, v15.4h}, [sp], 32
310 smull v12.4s, v4.4h, XFIX_1_175875602_MINUS_1_961570560
311 smlal v12.4s, v5.4h, XFIX_1_175875602
320 mov v8.16b, v12.16b
321 smlsl v12.4s, ROW5L.4h, XFIX_2_562915447
323 smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
331 add v2.4s, v2.4s, v12.4s
338 sub v2.4s, v2.4s, v12.4s
343 sub v2.4s, v2.4s, v12.4s
344 smull v12.4s, ROW2L.4h, XFIX_0_541196100_PLUS_0_765366865
346 smlal v12.4s, ROW6L.4h, XFIX_0_541196100
363 add v4.4s, v10.4s, v12.4s
366 sub v2.4s, v10.4s, v12.4s
367 add v12.4s, v4.4s, v14.4s
378 rshrn ROW0L.4h, v12.4s, #11
389 smull v12.4s, v10.4h, XFIX_1_175875602_MINUS_1_961570560
390 smlal v12.4s, v8.4h, XFIX_1_175875602
402 mov v8.16b, v12.16b
403 smlsl v12.4s, ROW5R.4h, XFIX_2_562915447
404 smlal v12.4s, ROW3R.4h, XFIX_3_072711026_MINUS_2_562915447
413 add v2.4s, v2.4s, v12.4s
421 sub v2.4s, v2.4s, v12.4s
424 sub v2.4s, v2.4s, v12.4s
425 smull v12.4s, ROW2R.4h, XFIX_0_541196100_PLUS_0_765366865
426 smlal v12.4s, ROW6R.4h, XFIX_0_541196100
436 add v4.4s, v10.4s, v12.4s
437 sub v2.4s, v10.4s, v12.4s
438 add v12.4s, v4.4s, v14.4s
444 rshrn ROW0R.4h, v12.4s, #11
458 smull v12.4S, ROW1R.4h, XFIX_1_175875602 /* ROW5L.4h <-> ROW1R.4h */
459 smlal v12.4s, ROW1L.4h, XFIX_1_175875602
460 smlal v12.4s, ROW3R.4h, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L.4h <-> ROW3R.4h */
461 smlal v12.4s, ROW3L.4h, XFIX_1_175875602_MINUS_1_961570560
469 mov v8.16b, v12.16b
470 smlsl v12.4s, ROW1R.4h, XFIX_2_562915447 /* ROW5L.4h <-> ROW1R.4h */
471 smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
476 add v2.4s, v2.4s, v12.4s
480 sub v2.4s, v2.4s, v12.4s
483 sub v2.4s, v2.4s, v12.4s
484 smull v12.4s, ROW2L.4h, XFIX_0_541196100_PLUS_0_765366865
485 smlal v12.4s, ROW2R.4h, XFIX_0_541196100 /* ROW6L.4h <-> ROW2R.4h */
495 add v4.4s, v10.4s, v12.4s
496 sub v2.4s, v10.4s, v12.4s
497 add v12.4s, v4.4s, v14.4s
503 shrn ROW0L.4h, v12.4s, #16
507 smull v12.4s, ROW5R.4h, XFIX_1_175875602
508 smlal v12.4s, ROW5L.4h, XFIX_1_175875602 /* ROW5L.4h <-> ROW1R.4h */
509 smlal v12.4s, ROW7R.4h, XFIX_1_175875602_MINUS_1_961570560
510 smlal v12.4s, ROW7L.4h, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L.4h <-> ROW3R.4h */
518 mov v8.16b, v12.16b
519 smlsl v12.4s, ROW5R.4h, XFIX_2_562915447
520 smlal v12.4s, ROW7L.4h, XFIX_3_072711026_MINUS_2_562915447 /* ROW7L.4h <-> ROW3R.4h */
525 add v2.4s, v2.4s, v12.4s
529 sub v2.4s, v2.4s, v12.4s
532 sub v2.4s, v2.4s, v12.4s
533 smull v12.4s, ROW6L.4h, XFIX_0_541196100_PLUS_0_765366865 /* ROW6L.4h <-> ROW2R.4h */
534 smlal v12.4s, ROW6R.4h, XFIX_0_541196100
544 add v4.4s, v10.4s, v12.4s
545 sub v2.4s, v10.4s, v12.4s
546 add v12.4s, v4.4s, v14.4s
552 shrn ROW4L.4h, v12.4s, #16 /* ROW4L.4h <-> ROW0R.4h */
567 ld1 {v12.4h, v13.4h, v14.4h, v15.4h}, [sp], 32
619 ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
654 smull v12.4s, ROW1L.4h, XFIX_1_175875602
655 smlal v12.4s, ROW3L.4h, XFIX_1_175875602_MINUS_1_961570560
660 mov v8.16b, v12.16b
661 smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
666 add v2.4s, v2.4s, v12.4s
667 add v12.4s, v12.4s, v12.4s
670 sub v2.4s, v2.4s, v12.4s
671 smull v12.4s, ROW2L.4h, XFIX_0_541196100_PLUS_0_765366865
679 add v4.4s, v10.4s, v12.4s
680 sub v2.4s, v10.4s, v12.4s
681 add v12.4s, v4.4s, v14.4s
687 shrn ROW0L.4h, v12.4s, #16
691 smull v12.4s, ROW5L.4h, XFIX_1_175875602
692 smlal v12.4s, ROW7L.4h, XFIX_1_175875602_MINUS_1_961570560
697 mov v8.16b, v12.16b
698 smlal v12.4s, ROW7L.4h, XFIX_3_072711026_MINUS_2_562915447
703 add v2.4s, v2.4s, v12.4s
704 add v12.4s, v12.4s, v12.4s
707 sub v2.4s, v2.4s, v12.4s
708 smull v12.4s, ROW6L.4h, XFIX_0_541196100_PLUS_0_765366865
716 add v4.4s, v10.4s, v12.4s
717 sub v2.4s, v10.4s, v12.4s
718 add v12.4s, v4.4s, v14.4s
724 shrn ROW4L.4h, v12.4s, #16 /* ROW4L.4h <-> ROW0R.4h */
805 * 4 | d24 | d25 ( v12.8h )
817 st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
825 ld1 {v12.8h, v13.8h}, [COEF_BLOCK], 32
830 mul v12.8h, v12.8h, v0.8h
857 sub v6.8h, v8.8h, v12.8h
858 add v12.8h, v8.8h, v12.8h
863 add v8.8h, v12.8h, v14.8h
865 sub v12.8h, v12.8h, v14.8h
880 sub v11.8h, v12.8h, v1.8h
885 add v12.8h, v12.8h, v1.8h
891 mov v18.16b, v12.16b
892 trn1 v12.8h, v12.8h, v13.8h
899 mov v18.16b, v12.16b
900 trn1 v12.4s, v12.4s, v14.4s
926 /* vswp v12.4h, v8-MSB.4h */
927 umov x22, v12.d[0]
928 ins v12.d[0], v8.d[1]
947 sub v6.8h, v8.8h, v12.8h
948 add v12.8h, v8.8h, v12.8h
953 add v8.8h, v12.8h, v14.8h
955 sub v12.8h, v12.8h, v14.8h
966 sub v11.8h, v12.8h, v1.8h
967 add v12.8h, v12.8h, v1.8h
974 sqshrn v10.8b, v12.8h, #5
1046 ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
1178 st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
1193 * 5 | v12.4h | v13.4h
1200 ld1 {v12.4h, v13.4h, v14.4h, v15.4h}, [COEF_BLOCK], 32
1219 mul v12.4h, v12.4h, v26.4h
1221 ins v12.d[1], v13.d[0] /* 128 bit q12 */
1231 idct_helper v4.4h, v6.4h, v8.4h, v10.4h, v12.4h, v14.4h, v16.4h, 12, v4.4h, v6.4h, v8.4h, v10.4h
1292 ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
1373 st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
1388 * 5 | v12.4h | v13.4h
1396 ld1 {v12.4h, v13.4h}, [COEF_BLOCK], 16
1414 mul v12.4h, v12.4h, v26.4h
1416 ins v12.d[1], v13.d[0]
1425 idct_helper v4.4h, v6.4h, v10.4h, v12.4h, v16.4h, 13, v4.4h, v6.4h
1432 smlal v26.4s, v12.4h, v14.h[1]
1481 ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
1552 st3 {v10.8b, v11.8b, v12.8b}, [RGB], 24
1554 st3 {v10.b, v11.b, v12.b}[0], [RGB], 3
1555 st3 {v10.b, v11.b, v12.b}[1], [RGB], 3
1556 st3 {v10.b, v11.b, v12.b}[2], [RGB], 3
1557 st3 {v10.b, v11.b, v12.b}[3], [RGB], 3
1559 st3 {v10.b, v11.b, v12.b}[4], [RGB], 3
1560 st3 {v10.b, v11.b, v12.b}[5], [RGB], 3
1562 st3 {v10.b, v11.b, v12.b}[6], [RGB], 3
1568 st4 {v10.8b, v11.8b, v12.8b, v13.8b}, [RGB], 32
1570 st4 {v10.b, v11.b, v12.b, v13.b}[0], [RGB], 4
1571 st4 {v10.b, v11.b, v12.b, v13.b}[1], [RGB], 4
1572 st4 {v10.b, v11.b, v12.b, v13.b}[2], [RGB], 4
1573 st4 {v10.b, v11.b, v12.b, v13.b}[3], [RGB], 4
1575 st4 {v10.b, v11.b, v12.b, v13.b}[4], [RGB], 4
1576 st4 {v10.b, v11.b, v12.b, v13.b}[5], [RGB], 4
1578 st4 {v10.b, v11.b, v12.b, v13.b}[6], [RGB], 4
1736 st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
1755 /* Initially set v10, v11.4h, v12.8b, d13 to 0xFF */
1822 ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
