Lines Matching full:machine
33 machine code for a specified target---either in assembly form (suitable for a
34 static compiler) or in binary machine code format (usable for a JIT
39 about various aspects of the machine, independently of how they will be used.
43 classes are intended to be abstract enough to represent the machine code for
44 *any* target machine. These classes are defined in
58 particular targets. These machine descriptions make use of the components
70 familiar with the `target description`_ and `machine code representation`_
75 target-description and machine code representation classes, ensuring that it is
96 GCC to emit machine code for a target.
101 for radically different targets that do not fit into the LLVM machine
128 3. `SSA-based Machine Code Optimizations`_ --- This optional stage consists of a
129 series of machine-code optimizations that operate on the SSA-form produced by
138 5. `Prolog/Epilog Code Insertion`_ --- Once the machine code has been generated
145 6. `Late Machine Code Optimizations`_ --- Optimizations that operate on "final"
146 machine code can go here, such as spill code scheduling and peephole
150 current function, either in the target assembler format or in machine
176 target machine, which allows the use of domain-specific and target-specific
195 directory) provide an abstract description of the target machine independent of
244 * which operations are natively supported by the target machine,
287 The ``TargetInstrInfo`` class is used to describe the machine instructions
323 Machine code description classes
326 At the high-level, LLVM code is translated to a machine specific representation
333 for machine code, as well as a register allocated, non-SSA form.
340 Target machine instructions are represented as instances of the ``MachineInstr``
341 class. This class is an extremely abstract way of representing machine
353 The operands of a machine instruction can be of several different types: a
355 addition, a machine operand should be marked as a def or a use of the value
381 Machine instructions are created by using the ``BuildMI`` functions, located in
383 functions make it easy to build arbitrary machine instructions. Usage of the
410 specify the number of operands that the machine instruction will take. This
441 The X86 instruction selector might produce this machine code for the ``div`` and
480 Some machine instructions, like calls, clobber a large number of physical
486 Machine code in SSA form
492 machine code PHI nodes, and virtual registers are only allowed to have a single
495 After register allocation, machine code is no longer in SSA-form because there
503 The ``MachineBasicBlock`` class contains a list of machine instructions
506 a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
515 The ``MachineFunction`` class contains a list of machine basic blocks
602 The MC Layer is used to represent and process code at the raw machine code
605 like label names, machine instructions, and sections in the object file. The
608 llvm-mc tool to implement standalone machine code assemblers and disassemblers.
630 higher level LLVM IR and Machine* constructs down to the MC layer, emitting
703 MCInst is the common currency used to represent machine instructions at the MC
724 code generator into target-specific machine instructions. There are several
762 (Machine Value Type) indicating what the type of the value is.
773 machine nodes have their chain after the instruction's operands, and
1130 .. _SSA-based Machine Code Optimizations:
1132 SSA-based Machine Code Optimizations
1189 and machine instructions. We then handle the "live-in" values. These are in
1192 ordering of the machine instructions ``[1, N]``. A live interval is an interval
1279 given machine operand is a register, use the boolean function
1352 With very rare exceptions (e.g., function calls), the LLVM machine code
1525 .. _Late Machine Code Optimizations:
1527 Late Machine Code Optimizations
1577 ops used by the code generator into the actual machine instructions they
1582 which lowers MCInst's into machine code bytes and relocations. This is
1593 enable the packetization of machine instructions.
1605 machine-independent API to determine if an instruction can be accommodated in a
1967 disassembling machine opcode bytes into MCInst's.
