Lines Matching full:getparent
62 if (Kills[i]->getParent() == MBB)
101 if (VRInfo.Kills[i]->getParent() == MBB) {
140 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
149 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
168 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
538 MachineBasicBlock *MBB = MI->getParent();
595 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
732 if (Def && Def->getParent() == &MBB)
744 Kills.insert(VI.Kills[i]->getParent());