Lines Matching defs:LRI
245 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
246 addKillFlag(*LRI);
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
249 PhysRegState[LRI->PhysReg] = regFree;
252 LiveVirtRegs.erase(LRI);
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
260 if (LRI != LiveVirtRegs.end())
261 killVirtReg(LRI);
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
270 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
271 spillVirtReg(MI, LRI);
276 LiveRegMap::iterator LRI) {
277 LiveReg &LR = *LRI;
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
297 LiveDbgValueMap[LRI->VirtReg];
324 killVirtReg(LRI);
508 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
509 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
510 assignVirtToPhysReg(*LRI, PhysReg);
511 return LRI;
516 LiveRegMap::iterator LRI,
518 const unsigned VirtReg = LRI->VirtReg;
538 // That invalidates LRI, so run a new lookup for VirtReg.
549 assignVirtToPhysReg(*LRI, PhysReg);
550 return LRI;
565 assignVirtToPhysReg(*LRI, *I);
566 return LRI;
575 // That invalidates LRI, so run a new lookup for VirtReg.
594 LiveRegMap::iterator LRI;
596 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
606 LRI = allocVirtReg(MI, LRI, Hint);
607 } else if (LRI->LastUse) {
610 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
611 addKillFlag(*LRI);
613 assert(LRI->PhysReg && "Register not assigned");
614 LRI->LastUse = MI;
615 LRI->LastOpNum = OpNum;
616 LRI->Dirty = true;
617 markRegUsedInInstr(LRI->PhysReg);
618 return LRI;
627 LiveRegMap::iterator LRI;
629 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
632 LRI = allocVirtReg(MI, LRI, Hint);
636 << PrintReg(LRI->PhysReg, TRI) << "\n");
637 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
639 } else if (LRI->Dirty) {
664 assert(LRI->PhysReg && "Register not assigned");
665 LRI->LastUse = MI;
666 LRI->LastOpNum = OpNum;
667 markRegUsedInInstr(LRI->PhysReg);
668 return LRI;
747 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
748 unsigned PhysReg = LRI->PhysReg;
756 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
757 PartialDefs.push_back(LRI->PhysReg);
770 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
771 unsigned PhysReg = LRI->PhysReg;
857 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
858 if (LRI != LiveVirtRegs.end())
859 setPhysReg(MI, i, LRI->PhysReg);
980 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
981 unsigned PhysReg = LRI->PhysReg;
984 killVirtReg(LRI);
1031 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1032 unsigned PhysReg = LRI->PhysReg;
