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Lines Matching full:issigned

2146 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2151   case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
2152   case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2153   case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2154   case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2155   case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2171   bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
2173   unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2177       !isDivRemLibcallAvailable(Node, isSigned, TLI))
2183     OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
2187     OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
2396   bool isSigned = (Opcode == ISD::SREM);
2406   if (isSigned) {
2446     unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;