Lines Matching full:issigned
112 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
114 unsigned NumOps, bool isSigned, SDLoc dl);
117 SDNode *Node, bool isSigned);
122 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
141 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
143 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
145 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
2196 bool isSigned) {
2204 Entry.isSExt = isSigned;
2205 Entry.isZExt = !isSigned;
2229 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2244 bool isSigned, SDLoc dl) {
2252 Entry.isSExt = isSigned;
2253 Entry.isZExt = !isSigned;
2264 .setSExtResult(isSigned).setZExtResult(!isSigned);
2276 bool isSigned) {
2286 Entry.isSExt = isSigned;
2287 Entry.isZExt = !isSigned;
2298 .setSExtResult(isSigned).setZExtResult(!isSigned);
2323 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2338 return ExpandLibCall(LC, Node, isSigned);
2346 bool isSigned = Opcode == ISD::SDIVREM;
2351 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2352 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2353 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2354 isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2355 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2373 Entry.isSExt = isSigned;
2374 Entry.isZExt = !isSigned;
2382 Entry.isSExt = isSigned;
2383 Entry.isZExt = !isSigned;
2393 .setSExtResult(isSigned).setZExtResult(!isSigned);
2519 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2543 if (isSigned) {
2564 SDValue Bias = DAG.getConstantFP(isSigned ?
2584 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2585 // Code below here assumes !isSigned without checking again.
2618 if (!isSigned) {
2732 bool isSigned,
2749 if (isSigned) continue;
2763 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2774 bool isSigned,
2794 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
3452 bool isSigned = Node->getOpcode() == ISD::SREM;
3453 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3454 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3472 bool isSigned = Node->getOpcode() == ISD::SDIV;
3473 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3605 bool isSigned = Node->getOpcode() == ISD::SMULO;
3606 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3608 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3609 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3610 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3614 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3615 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3654 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3667 if (isSigned) {
