Lines Matching refs:regB
109 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
115 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
119 unsigned RegA, unsigned RegB, unsigned Dist);
534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
535 if (RegA == RegB)
537 if (!RegA || !RegB)
539 return TRI->regsOverlap(RegA, RegB);
547 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
585 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
591 // -RegB is not tied to a register and RegC is compatible with RegA.
592 // -RegB is tied to the wrong physical register, but RegC is.
593 // -RegB is tied to the wrong physical register, and RegC isn't tied.
597 // -RegC is not tied to a register and RegB is compatible with RegA.
598 // -RegC is tied to the wrong physical register, but RegB is.
599 // -RegC is tied to the wrong physical register, and RegB isn't tied.
610 // If there is a use of regB between its last def (could be livein) and this
613 if (!noUseAfterLastDef(regB, Dist, LastDefB))
634 if (isRevCopyChain(regB, regA, 3))
675 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
682 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
694 unsigned RegA, unsigned RegB,
711 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
713 // uses RegB, convertToThreeAddress must have created more
715 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
727 DstRegMap.erase(RegB);
1223 unsigned regB = MI.getOperand(SrcIdx).getReg();
1225 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1227 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1248 // If there is one more use of regB later in the same MBB, consider
1250 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1255 // If we commuted, regB may have changed so we should re-sample it to avoid
1258 regB = MI.getOperand(SrcIdx).getReg();
1259 regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1265 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1267 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1278 // If there is one more use of regB later in the same MBB, consider
1280 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1332 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1461 unsigned RegB = 0;
1470 // Grab RegB from the instruction because it may have changed if the
1472 RegB = MI->getOperand(SrcIdx).getReg();
1475 if (RegA == RegB) {
1484 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1502 MIB.addReg(RegB, 0, SubRegB);
1503 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1513 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1539 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1548 TargetRegisterInfo::isVirtualRegister(RegB))
1557 SrcRegMap[RegA] = RegB;
1562 // Replace other (un-tied) uses of regB with LastCopiedReg.
1564 if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
1576 // Update live variables for regB.
1577 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1580 LV->addVirtualRegisterKilled(RegB, PrevMI);
1585 LiveInterval &LI = LIS->getInterval(RegB);
1588 assert(I != LI.end() && "RegB must be live-in to use.");
1596 // Some tied uses of regB matched their destination registers, so
1597 // regB is still used in this instruction, but a kill flag was
1598 // removed from a different tied use of regB, so now we need to add
1599 // a kill flag to one of the remaining uses of regB.
1601 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
