Home | History | Annotate | Download | only in AArch64

Lines Matching defs:TRI

117   const TargetRegisterInfo *TRI;
319 TRI = F.getRegInfo().getTargetRegisterInfo();
501 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));
505 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID));
514 MCRegAliasIterator AI(J.getReg(), TRI, /*IncludeSelf=*/true);
529 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
554 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
630 << TRI->getName(DestReg) << " at " << *MI);
650 << TRI->getName(AccumReg) << " in MI " << *MI);
675 << TRI->getName(DestReg) << "\n");
703 DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg())
715 << TRI->getName(I->first) << "\n");
726 if ((TRI->getEncodingValue(Reg) % 2) == 0)