Lines Matching defs:AddReg
349 ResultReg).addReg(ZeroReg, getKillRegState(true));
387 .addReg(TmpReg, getKillRegState(true));
406 .addReg(ADRPReg)
439 .addReg(ADRPReg)
454 .addReg(ADRPReg)
1077 MIB.addReg(Addr.getReg());
1078 MIB.addReg(Addr.getOffsetReg());
1082 MIB.addReg(Addr.getReg()).addImm(Offset);
1272 .addReg(LHSReg, getKillRegState(LHSIsKill))
1273 .addReg(RHSReg, getKillRegState(RHSIsKill));
1316 .addReg(LHSReg, getKillRegState(LHSIsKill))
1357 .addReg(LHSReg, getKillRegState(LHSIsKill))
1358 .addReg(RHSReg, getKillRegState(RHSIsKill))
1400 .addReg(LHSReg, getKillRegState(LHSIsKill))
1401 .addReg(RHSReg, getKillRegState(RHSIsKill))
1459 .addReg(LHSReg, getKillRegState(LHSIsKill));
1470 .addReg(LHSReg, getKillRegState(LHSIsKill))
1471 .addReg(RHSReg, getKillRegState(RHSIsKill));
1836 .addReg(ResultReg, getKillRegState(true))
2055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
2258 .addReg(SrcReg, getKillRegState(SrcIsKill));
2389 .addReg(ConstrainedCondReg, getKillRegState(CondRegIsKill))
2406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
2432 .addReg(AArch64::WZR, getKillRegState(true));
2472 .addReg(AArch64::WZR, getKillRegState(true))
2473 .addReg(AArch64::WZR, getKillRegState(true))
2477 .addReg(TmpReg1, getKillRegState(true))
2478 .addReg(AArch64::WZR, getKillRegState(true))
2491 .addReg(AArch64::WZR, getKillRegState(true))
2492 .addReg(AArch64::WZR, getKillRegState(true))
2662 .addReg(CondReg, getKillRegState(CondIsKill))
2697 ResultReg).addReg(Op);
2713 ResultReg).addReg(Op);
2747 .addReg(SrcReg);
2897 .addReg(DstReg, getKillRegState(true));
2957 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3022 .addReg(RVLocs[0].getLocReg());
3107 MIB.addReg(Reg);
3121 .addReg(ADRPReg)
3134 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
3139 MIB.addReg(Reg, RegState::Implicit);
3314 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
3457 .addReg(SrcReg, getKillRegState(SrcRegIsKill));
3623 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3723 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3732 MIB.addReg(RetReg, RegState::Implicit);
3795 .addReg(SrcReg, getKillRegState(SrcIsKill));
3820 .addReg(ResultReg)
3925 .addReg(Op0, getKillRegState(Op0IsKill));
3973 .addReg(Op0, getKillRegState(Op0IsKill))
4032 .addReg(Op0, getKillRegState(Op0IsKill));
4094 .addReg(Op0, getKillRegState(Op0IsKill))
4153 .addReg(Op0, getKillRegState(Op0IsKill));
4203 .addReg(Op0, getKillRegState(Op0IsKill))
4262 .addReg(SrcReg)
4359 .addReg(Reg, getKillRegState(true))
4402 .addReg(SrcReg, getKillRegState(SrcIsKill))
4742 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne);
4743 if (!AddReg)
4760 fastEmitInst_rri(SelectOpc, RC, AddReg, /*IsKill=*/true, Src0Reg,
